Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage.

Abstract: A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time.

Abstract: A semiconductor memory device includes a semiconductor substrate having a channel therein; a gate insulating layer formed of a ferroelectric material provided on the semiconductor substrate; and a gate electrode provided on the gate insulating layer. The ferroelectric material includes a nitrogen (N) and at least one element selected from the group consisting of Mg, Sr, Ba and Ca.

Abstract: A lower carbon film as a provisional film, a lower SiO2 film and an upper carbon film are formed, and then trenches having a wiring pattern are formed in the upper carbon film. Next, contact holes are formed through the lower carbon film and the lower SiO2 film. Then, wires and plugs are formed by filling in the trenches and contact holes with a barrier metal film and a Cu alloy film. After these process steps are repeatedly performed several times, a dummy opening is formed to extend downward through the uppermost SiO2 film. Thereafter, the carbon films are removed by performing ashing with oxygen introduced through the dummy opening. As a result, gas layers are formed to surround the wires and plugs. In this manner, a highly reliable gas-dielectric interconnect structure can be obtained by performing simple process steps.

Abstract: A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower volt age. Also, since the select transistor is provided, reading c an also be performed at a lower voltage.

Abstract: While conventionally, a Co film is deposited by directional sputtering directly on a source/drain diffusion layer formed on the surface of an Si substrate while the substrate is being heated, a thin oxide film is formed on the source/drain diffusion layer and then, the Co film is deposited by directional sputtering while the substrate is being heated. By doing this, an inner Co—Si layer the composition of which is thermally unstable is formed and a Co—Si—O layer is formed on the Co—Si layer. After the remaining unreacted Co film and the Co—Si—O layer are selectively removed, a high-temperature heat treatment is performed, so that the inner Co—Si layer is transformed into a CoSi2 layer to increase the film thickness. The formation of the oxide film curbs the speed of reaction between Co and Si, so that a Co—Si layer of the same thickness as that in the wide region can be formed in the fine region.

Abstract: It is an object of the present invention to reduce variations in dimensional accuracy such as the outer-diameter accuracy and roundness of a flare shape and the concentricity between the bulb portion and the flare portion. According to the present invention, a lower mold (1) formed of a metallic material and forming a recess flare shape (1a) that is subjected to surface treatment forms a flare shape (21b) almost identical to the flare shape (1a) by means of the rotational motion of a rotating head portion (2). An upper mold (10) is fitted in the lower mold (1) to form a flare-shaped gap portion (13), into which glass is forced to form a flare shape (22).

Abstract: An electronic device which improves speed of signal transmission in a bus wiring system by specifying circuit configuration of a driver circuit and transmission line characteristic impedance. An input/output circuit combines a differential driver of current switch type with a bus wiring system having a transmission line for transmitting a differential complementary digital signal and a termination end resistor matching the transmission line. An integrated circuit chip including the differential driver is mounted on a wiring board including the transmission line and the termination end resistor. The transmission line includes wires having an equal length which have characteristic impedance of 25&OHgr; or less. In combination with the current switch type differential driver, this transmission line structure restricts attenuation of signal energy during transmission and restricts electromagnetic interference between transmission lines close to each other.

Abstract: A lighting unit with a reflecting mirror to prevent irradiation nonuniformity on an irradiated surface, produced by arranging a bulb as a light source in a funnel-shaped reflecting mirror having a reflecting surface and by arranging a plurality of fine reflecting surfaces on the reflecting surface non-radially and non-concentrically without clearance. Preferably the fine reflecting surfaces appear to be a honeycomb, and are formed substantially the same size of 0.01-5 mm long, 0.01-5 mm wide.

Abstract: An apparatus for plasma etching comprises a chamber, a gas inlet port provided in the chamber to introduce etching gas into the chamber, a gas outlet port provided in a side portion of the chamber to exhaust the gas from said chamber, a sample stage provided within the chamber, and a spiral coil disposed externally of the chamber and in opposing relation with the sample stage to generate a plasma composed of the etching gas with a high-frequency induction field. The higher-voltage region of the spiral coil and the exhaust-side region of the sample stage are positioned on substantially the same side relative to the center axis of the chamber.

Abstract: A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen barrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper and

Abstract: A long life microwave electrodeless discharge lamp apparatus capable of preventing the generation of noise. The microwave electrodeless discharge lamp apparatus includes a magnetron having a magnetron tube and a yoke that surrounds the magnetron tube, a container housing at least the magnetron tube, a waveguide in which microwaves oscillated by the magnetron are propagated, an electrodeless discharge tube sealing luminescent materials excited by the microwaves to emit light, wherein a space surrounded by the yoke is communicated with the inside of the container, and wherein a fluid is sealed in the container. Thus, the magnetron tube is in a state in which it is immersed in the fluid.

Abstract: An electronic device such as a semiconductor device, a method of manufacturing the same, and an apparatus for manufacturing the same, wherein by placing a ceramic substrate provided with a metallic thin film integrated into at least one selected from an upper surface and a lower surface of the ceramic substrate in its peripheral portion so as to extend both inside and outside a cavity of a mold for transfer molding, and positioning the metallic thin film in a position with which an upper mold and a lower mold of the mold come into contact, occurrence of cracks or breakage in the ceramic substrate is prevented by buffering the pressure applied to the ceramic substrate so as to prevent a distortion force from being caused even when the ceramic substrate is sandwiched and compressed between the upper mold and the lower mold.

Abstract: A cathode ray tube capable of reducing the doming amount and suppressing the occurrence of moire stripes at the same time with improved effects to suppress the occurrence of moire stripes even more is provided. The protruding portions 28a, 28b are protruding from the ends of the horizontal direction of the aperture to the inside of the aperture 27. With regard to the horizontal cross sections of the protruding portions 28a, 28b, the portions facing each other left and right via the aperture are formed to be asymmetrical to the center line 29 in order to reduce or block the incident electron beam. By forming the protruding portions 28a, 28b, the doming amount can be reduced and the occurrence of moire stripes can be suppressed at the same time. Furthermore, by forming the portions facing each other left and right of the protruding portions asymmetrically, the effects to suppress the occurrence of moire stripes can be improved even more.

Abstract: A first magnet that generates a magnetic field having the same polarity as that generated by a vertical deflection coil during a deflection toward the upper side is provided on a phosphor screen side of the deflection coil and above a horizontal axis. A second magnet that generates a magnetic field having the same polarity as that generated by the vertical deflection coil during a deflection toward the lower side is provided on a phosphor screen side of the deflection coil and below the horizontal axis. A third magnet that generates a magnetic field having the opposite polarity to that generated by the vertical deflection coil during the deflection toward the upper side is provided on the phosphor screen side with respect to the first and second magnets and above the horizontal axis.

Abstract: A lead frame used for a resin-sealed semiconductor device includes a die-mount portion on which a semiconductor chip rests; and a plurality of leads arranged along a common portion of the lead frame. The plurality of leads include at least one adjusting lead, and the adjusting lead has a length that is less than the others of the plurality of leads such that a tip of the adjusting lead is sufficiently proximate to an outer peripheral surface of a resin-seal body to prevent resin flash during a formation of the semiconductor device and to allow the adjusting lead to be removed after the resin-seal body is formed over a portion of the lead frame.

Abstract: A resist composition comprising an alkali-soluble polymer, a special cross-linking agent containing one or more oxirane rings and at least one of —O—, —CO—,—COO— and —OCO— groups in the molecule, a photoacid generator, and a solvent can form a film having high transmittance for deep UV light such as ArF excimer laser beams and high etching resistance as well as high resolution, and thus suitable for forming a negative working pattern.

Abstract: A lower carbon film as a provisional film, a lower SiO2 film and an upper carbon film are formed, and then trenches having a wiring pattern are formed in the upper carbon film. Next, contact holes are formed through the lower carbon film and the lower SiO2 film. Then, wires and plugs are formed by filling in the trenches and contact holes with a barrier metal film and a Cu alloy film. After these process steps are repeatedly performed several times, a dummy opening is formed to extend downward through the uppermost SiO2 film. Thereafter, the carbon films are removed by performing ashing with oxygen introduced through the dummy opening. As a result, gas layers are formed to surround the wires and plugs. In this manner, a highly reliable gas-dielectric interconnect structure can be obtained by performing simple process steps.

Abstract: A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen carrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper and

Abstract: A liquid precursor for forming a layered superlattice material is applied to an integrated circuit substrate. The precursor coating is annealed in oxygen using a rapid ramping anneal (“RRA”) technique with a ramping rate of 50° C./second at a hold temperature of 650° C. for a holding time of 30 minutes.