Abstract: There is provided a method for processing data sets in a processor. The processor has a pipelined data path including an input, an output, and at least one discrete stage. The pipeline is configured to enable one or more data sets, each comprising one or more data items, to enter the pipeline from the input, propagate through the pipeline, and exit the pipeline through the output. Each discrete stage represents an operation to be performed on the data item occupying the discrete stage. The method comprises defining one or more non-overlapping sections of the pipeline corresponding to portions of the pipeline occupied by the data items of at least one data set. In addition, the method comprises providing one or more logic units, each dedicated to control the progress of the data items of the at least one data set through the pipeline as the section advances through the pipeline.

Abstract: A method of generating a hardware design for a pipelined parallel stream processor, by defining a hardware processing operation; specifying at least one propagation rule; defining a graph representing the processing operation in the time domain, comprising at least one data path to be implemented as a hardware design and a plurality of parallel branches; each data path having: at least one data path input, output, and discrete object corresponding to a hardware element; each discrete object comprises an input for receiving an input variable, an operator for executing a function on said input variable, and an output variable; optimizing each output from each discrete object in dependence upon the propagation rule to produce an optimised graph; and utilizing the optimised graph to define an optimised hardware design for implementation in said pipelined parallel stream processor.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Abstract: A method of generating a hardware design for a stream processor. The method includes defining a graph representing a processing operation designating processes to be implemented in hardware as part of the stream processor. The graph represents the processing operation in the time domain as a function of clock cycles and includes at least one data path. At least one stream offset object is provided located at a particular point in the data path.

Abstract: There is provided embodiment of methods of and apparatus for generating a hardware design for a pipelined parallel stream processor.

Abstract: A method of generating a hardware design for a pipelined parallel stream processor, by defining a hardware processing operation; specifying at least one propagation rule; defining a graph representing the processing operation in the time domain, comprising at least one data path to be implemented as a hardware design and a plurality of parallel branches; each data path having: at least one data path input, output, and discrete object corresponding to a hardware element; each discrete object comprises an input for receiving an input variable, an operator for executing a function on said input variable, and an output variable; optimizing each output from each discrete object in dependence upon the propagation rule to produce an optimised graph; and utilizing the optimised graph to define an optimised hardware design for implementation in said pipelined parallel stream processor.

Abstract: Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node.

Abstract: Embodiments of the invention provide a method and apparatus for generating programmable logic for a hardware accelerator, the method comprising: generating a graph of nodes representing the programmable logic to be implemented in hardware; identifying nodes within the graph that affect external flow control of the programmable logic; retaining the identified nodes and removing or replacing all nodes which do not affect external flow control of the programmable logic in a modified graph; and simulating the modified graph or building a corresponding circuit of the retained nodes.

Abstract: There is provided embodiment of methods of generating a hardware design for a pipelined parallel stream processor.

Abstract: Embodiments of the invention provide a method of automatically generating a hardware stream processor design including plural processes and interconnect between the plural processes to provide data paths between the plural processes, the method comprising: providing an input designating processes to be performed by the stream processor; automatically optimizing parameters associated with the interconnect between processes within the design so as to minimise hardware requirements whilst providing the required functionality; and generating an optimized design in accordance with the optimization.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.

Abstract: There is provided a method of, and apparatus for, processing a computation on a computing device comprising at least one processor and a memory, the method comprising: storing, in said memory, plural copies of a set of data, each copy of said set of data having a different compression ratio and/or compression scheme; selecting a copy of said set of data; and performing, on a processor, a computation using said selected copy of said set of data. By providing such a method, different compression ratios and/or compression schemes can be selected as appropriate. For example, if high precision is required in a computation, a copy of the set of data can be chosen which has a low compression ratio at the expense of processing time and memory transfer time. In the alternative, if low precision is acceptable, then the speed benefits of a high compression ratio and/or lossy compression scheme may be utilised.

Abstract: There is provided a method of processing an iterative computation on a computing device comprising at least one processor. Embodiments of the method comprises performing, on a processor, an iterative calculation on data in a fixed point numerical format having a scaling factor, wherein the scaling factor is selectively variable for different steps of said calculation in order to prevent overflow and to minimise underflow. By providing such a method, the reliability, precision and flexibility of floating point operations can be achieved whilst using fixed point processing logic. The errors which fixed-point units are usually prone to generate if the range limits are exceeded can be mitigated, whilst still providing the advantage of a significantly reduced logic area to perform the calculations in fixed point.

Abstract: The invention provides a method of transferring data from a data array within a main memory of a computer to an accelerator for processing, the embodiment of the method comprising: at the accelerator, requesting data from the main memory and generating a data stream between the main memory and the accelerator, the generated data stream including data from the data array; and, using an offset to determine the scheduling of array elements within the generated data stream.