Abstract: Dynamic error-quantizer tuning systems and methods prevent misconvergence to local minima by using a dynamic quantizer circuit that controls reference voltages of three or more comparators that are independently adjusted to modify the transfer function of the dynamic quantizer circuit. A weighted sum of the comparator outputs is subtracted from the input to form an error signal in a control loop. The ratio of the reference voltages is chosen to reduce or eliminate local minima during a convergence of the control loop and is set to values that minimize a mean squared error signal with respect to discrete modulation states of the input after the convergence of the control loop is complete.

Abstract: Presented are systems and methods for improving transient response in buck-boost circuits avoid circuit instabilities in both boost mode and buck mode. In embodiments, this is accomplished when, in response to determining that the circuit operates in buck mode, a compensation circuit is adjusted to operate at a first bandwidth. In response to determining that the circuit operates in boost mode, the compensation circuit may then be adjusted to decrease a boost mode crossover frequency and operate at a second, lower bandwidth.

Abstract: Presented are systems and methods for controlling a compensation circuit. In embodiments, a detection circuit receives a set of control signals that have been generated by a control circuit to drive a set of light emitting diode (LED) switches. The switches control a set of LEDs driven by a DC-DC converter that is coupled to a feedback loop to which the compensation circuit is removably coupled. In embodiments, the detection circuit determines whether the status of an LED is about to change and, in response, uses the compensation circuit to control the feedback loop in a manner such as to reduce a current overshoot or current undershoot in the LED current.

Abstract: A digital communication station includes a coupled inductor, driver circuitry, and a digital transceiver. The coupled inductor includes (1) a first winding connected between a first digital communication node and a first power node, (2) a second winding connected between a second digital communication node and a second power node, and (3) a third winding. The driver circuitry is configured to drive the third winding to increase respective inductance values of the first and second windings, and the digital transceiver is communicatively coupled to the first digital communication node and the second digital communication node.

Abstract: The invention relates to an electronic device, and more particularly, to systems, devices and methods of authenticating the electronic device using a challenge-response process that is based on a physically unclonable function (PUF). The electronic device comprises a PUF element, a processor and a communication interface. The PUF element generates an input signal based on at least one PUF that has unique physical features affected by manufacturing variability. A challenge-response database, comprising a plurality of challenges and a plurality of corresponding responses, is set forth by the processor based on the PUF-based input and further provided to a trusted entity. During the trusted transaction, the processor generates a response in response to a challenge sent by the trusted entity based on the PUF-based input, and thereby, the trusted entity authenticates the electronic device by comparing the response with the challenge-response database.

Abstract: A switching power converter includes an integrated inductor assembly, a first switching stage, and a second switching stage. The integrated inductor assembly includes a magnetic core and first and second windings disposed at least partially in the magnetic core. The second winding is separated from the first winding by a separation portion of the magnetic core. The first switching stage is configured such that a first current flowing from the first switching stage to the first winding induces first magnetic flux flowing through the separation portion of the magnetic core. The second switching stage is configured such that a second current flowing from the second switching stage to the second winding induces second magnetic flux flowing through the separation portion of the magnetic core that opposes the first magnetic flux in the separation portion of the magnetic core.

Abstract: An inductor includes a magnetic core, a first winding, a first electrically conductive standoff, and a second electrically conductive standoff. The magnetic core includes opposing first and second outer surfaces separated from each other in a first direction. The first winding has first and second ends, and the first winding is wound around at least a portion of the magnetic core. The first electrically conductive standoff is connected to the first end of the first winding, and the first electrically conductive standoff extends along the magnetic core in the first direction from the first outer surface to the second outer surface. The second electrically conductive standoff is connected to the second end of the first winding, and the second electrically conductive standoff extends along the magnetic core in the first direction from the first outer surface to the second outer surface.

Abstract: A circuit assembly includes a first substrate including a first outer surface, a first capacitor disposed on the first outer surface, and a first metallic bar. The first capacitor has a first capacitor thickness in a first direction orthogonal to the first outer surface. The first metallic bar has a first bar thickness in the first direction, the first bar thickness being greater than the first capacitor thickness. An electrical load is optionally disposed on a second outer surface of the first substrate over the first metallic bar, in the first direction. The electrical load may be electrically coupled to the first metallic bar.

Abstract: Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.

Abstract: Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may communicate the fault detection code to a controller. Once the transceiver input receives a second signal, the fault pin voltage may be reset to clear the fault detection code before resuming operations, including detecting additional fault conditions as they arise.

Abstract: A time of flight sensor includes a time of flight (TOF) processor having a digital TOF port, a digital input port, and a digital output port, the TOF processor comprising a phase detector including cyclically rotating demultiplexer (DEMUX), a first summer coupled to a first DEMUX output, a second summer coupled to a second DEMUX output, a third summer coupled to a third DEMUX output, a fourth summer coupled to a fourth DEMUX output, and a phase estimator coupled to outputs of the first summer, the second summer, the third summer and the fourth summer and having a phase estimate output; a driver having a digital driver port coupled to the digital TOF port and a driver output port; and an analog-to-digital converter (ADC) having an output port coupled to the digital input port of the digital TOF processor.

Abstract: A sensor offset voltage compensation circuit includes a programmable gain amplifier (PGA) having an input loop configured to receive the signal output by a sensor (e.g., a voltage generated a sensor resistive bridge of a pressure sensor) and an output loop configured to furnish an output signal having a voltage that is greater than the input voltage. An offset compensation voltage is applied to at least one of the input loop or the output loop of the PGA to at least substantially cancel the zero-quantity offset voltage of the sensor from the output voltage.

Abstract: Dynamic error-quantizer tuning systems and methods prevent misconvergence to local minima by using a dynamic quantizer circuit that controls reference voltages of three or more comparators that are independently adjusted to modify the transfer function of the dynamic quantizer circuit. A weighted sum of the comparator outputs is subtracted from the input to form an error signal in a control loop. The ratio of the reference voltages is chosen to reduce or eliminate local minima during a convergence of the control loop and is set to values that minimize a mean squared error signal with respect to discrete modulation states of the input after the convergence of the control loop is complete.

Abstract: Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.

Abstract: In-flight operations in an inbound data path from a source memory to a convolution hardware circuit increase computational throughput when performing convolution calculations, such as pooling and element-wise operations. Various operations may be performed in-line within an outbound data path to a target memory. Advantageously, this drastically reduces extraneous memory access and associated read-write operations, thereby, significantly reducing overall power consumption in a computing system.

Abstract: Presented are average current mode control systems and methods for driving a load with a constant current. In embodiments, this is accomplished when, in response to a zero-current detection circuit detecting a zero current condition in the load current, a compensation circuit is disconnected from a first error amplifier to enable that error amplifier to provide a first voltage to a second error amplifier. The second error amplifier increases a charging current in a capacitor to reduce a dead time in the load current. Similarly, in response to an overcurrent detection circuit detecting an overcurrent condition in the load current, the compensation circuit is disconnected from the first error amplifier to enable the first error amplifier to provide a second voltage to the second error amplifier to decrease the charging current and reduce an overshoot condition.

Abstract: A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

Abstract: Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.

Abstract: Described is a method and a circuit arrangement for controlling a stepper motor in a voltage-controlled or voltage-regulated operating mode, having a bridge circuit provided for a motor coil (A) with semiconductor switches (HS1, HS2, LS1, LS2) for applying a first and a second PWM voltage (U(LA1), U(LA2)) having opposite polarity to the motor coil (A) and having a charge pump for switching at least the high-side semiconductor switch (HS1, HS2) of the bridge circuit. Because the charge pump must wait for a blocking or dead time before a further semiconductor switch can be switched after switching a first semiconductor switch, the time interval between a rising edge of one of the two PWM voltages and a subsequent rising edge of the respective other PWM voltage is increased at least until the blocking or dead time of the charge pump has elapsed.

Abstract: An angle-of-arrival antenna system uses two orthogonal arrays of patch antenna elements to measure the angle of arrival of a wireless signal irrespective of its polarization. Each antenna element has an antenna patch located over a corresponding ground patch. A shorting wall directly electrically connects one edge of the antenna patch to a corresponding edge of the underlying ground patch. The edge of the ground patch is also directly connected to a system ground plane. No other edges of the ground patch are connected to the system ground plane. The shorting wall acts as an impedance that isolates the ground patch from the system ground plane, and therefore improves isolation between the antenna elements. The antenna system may be constructed using conventional circuit-board fabrication techniques by implementing each shorting wall as an array of plated through-holes or slots.