Abstract: A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output.

Abstract: A circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined voltage level. A first stage set of capacitors is operatively coupled to the level-crossing detector. A ramp circuit is operatively coupled to the set of series-connected capacitors. A second stage set of capacitors is operatively coupled to the first stage set of capacitors and the ramp circuit. The ramp circuit includes a feedback capacitor and a preset switch to provide a linear ramp output.

Abstract: Various embodiments allow for background calibration of channel-to-channel mismatch errors. In certain embodiments calibration is accomplished by comparing the output of I-ADCs against the output of a reference ADC and correlating the difference to a known function to obtain a correction signal that can be used to correct channel-to-channel mismatch errors.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: In an example embodiment a headset includes a phone jack, a speaker connected to the phone jack, a microphone coupled to the phone jack and a resistive switch string coupled to the phone jack to the same ring of the phone jack as the microphone. In another example an integrated circuit device includes a charge pump, a multi-voltage LDO having an input which is capable of being coupled to an output of the charge pump, an ADC; and a pull-up resistor coupled between an output of the LDO and an input of the ADC. In another example embodiment, a method for headset signal multiplexing includes providing a headset with a plurality of signal sources and voltage division multiplexing the plurality of signal sources on a common wire.

Abstract: A current share system for providing current to a load includes a first power supply module that controls a first voltage converter to provide a first current to the load, that transmits synchronization information using a first pin, and that transmits at least one second type of information using the first pin. A second power supply module receives the synchronization information at a second pin, receives the at least one second type of information at the second pin, and controls a second voltage converter to provide a second current to the load based on the synchronization information and the at least one second type of information.

Abstract: An embodiment is a method and apparatus to estimate channel quality. An absolute processor computes absolute real and imaginary values of real and imaginary parts, respectively, of output of a demodulator. A phase count unit generates first and second phase counts representing deviations from zero phase noise using the absolute real and imaginary values. An amplitude count unit generates first and second amplitude counts representing attenuation of a received signal using the absolute real and imaginary values. An integrator integrates the first and second phase counts and first and second amplitude counts into a signal quality indicator that represents a measure of quality of channel with respect to noise and fading.

Abstract: A transceiver for an ultrasonic imaging device includes a transmit circuit and a receive circuit. The transmit circuit outputs test pulses to a probe including a transducer to generate an image of a test object. A composite signal including the test pulses and a reflected signal is output by the transducer. The receive circuit receives the composite signal including the test pulses and the reflected signal and includes a filter circuit. The filter circuit filters the test pulses from the composite signal and passes the reflected signal. An impedance of the filter circuit is equal to substantially zero when the reflected signal is within a predetermined frequency range.

Abstract: Various embodiments of the invention relate generally to real-time clock circuit, and more particularly to systems, devices and methods of integrating two oscillators in one real-time clock circuit to generate accurate time of day over an industrial temperature range. A primary oscillator is employed to generate a first high precision clock while having a higher frequency and consuming more power; a secondary oscillator is employed to generate a second clock that has a low frequency and consumes less power, but may not meet the time accuracy requirement. When the real-time clock is provided with sufficient power (MSN mode), time of day is constantly tracked by the primary oscillator, but when the real-time clock is powered by a battery (SLEEP mode), time of day is tracked by the secondary oscillator while the primary oscillator is switched on at an update frequency to compensate errors in the time of day.

Abstract: A first control system for a power supply includes a switch-mode DC-DC converter module and an FET gate drive module. The switch-mode DC-DC converter module receives an input voltage and generates first and second voltages, the first voltage powering a DC-DC control module. The FET gate drive module selectively drives a plurality of FETs of the power supply using the second voltage thereby generating a desired output voltage from the input voltage. A second control system is directed to driving the second voltage to a desired gate voltage, wherein the desire gate voltage is determined based on at least one of a plurality of operating parameters. A third control system includes controlling first and second voltages generated by a SIDO voltage converter based on the first and second voltages and a damping factor, and generating the damping factor based on current flowing through the inductor of the SIDO voltage converter.

Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.

Abstract: A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board.

Abstract: An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet.

Abstract: A method to control weighted prediction for video compression. The method comprises (A) generating statistics based upon analysis of a plurality of video frames, (B) detecting a fade condition based upon the statistics, (C) generating one or more estimated weighted prediction parameters based upon the statistics when the fade condition is detected and (D) encoding the plurality of video frames. The encoding takes into account the estimated weighted prediction parameters when generated.

Abstract: A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown.

Abstract: Embodiments of the present invention provide systems, devices and methods for detecting both ambient light and proximity to an object. This detection is performed by a double-layered photodiode array and corresponding circuitry such that ambient light and proximity detection are enabled by a plurality of integrated photodiodes. In various embodiments of the invention, ambient light is sensed using a first set of photodiodes and a second set of photodiodes such that a spectral response is created that is approximately equal to the visible light spectrum. Proximity detection is realized using an integrated photodiode, positioned below the first and second sets of photodiodes, that detects infrared light and generates a response thereto.

Abstract: The present disclosure includes a power measurement, circuit breaker or integrated protection system including isolated analog-to-digital modulators for measuring current using current sensors, such as, for example, current shunts, in a single or multiphase power system. In one embodiment, the modulators are divided into a line-side device with an analog-to-digital modulator and a host-side device including a decimation filter and a processor. In one embodiment, an isolation barrier, such as, for example, a pulse transformer, divides the lineside device from the host-side device.

Abstract: An apparatus for transferring data in a non-spread domain to a spread domain. The apparatus comprises a first-in-first-out (FIFO) memory; a write pointer generator adapted to generate a write pointer for writing data into the FIFO memory in response to a non-spread clock signal; a spread-clock generator adapted to generate a spread clock signal based on the non-spread clock signal; a read pointer generator adapted to generate a read pointer for reading data from the FIFO memory in response to the spread clock signal; and a controller adapted to control the spread-clock generator in response to the read and write pointers indicating predetermined potential data overflow or underflow of the FIFO memory.

Abstract: A method and apparatus for detection of load impedance modulation as a result of communication of data from the secondary to the primary side of a transformer are presented. The load impedance on the secondary of the transformer barrier is modulated differentially using data to be communicated across the barrier. A detection circuit on the primary side isolates the load current from the magnetizing current in the primary. The load current is subsequently integrated over two consecutive Manchester periods and the integrated value from the first Manchester period is compared against that of the second period thereby recovering the receive data.

Abstract: A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.