Abstract: A method includes determining an address associated with a data transform command in a container data structure which is in a host computing unit. The host computing unit is in communication with the data transform accelerator. In response to a determination that the address is in the container data structure, the method includes accessing the data transform command based on the address. The method also includes obtaining metadata based on information in the data transform command. The metadata is in the host computing unit. The metadata can be shared in its entirety or partially by multiple data transform commands grouped together. The method further includes configuring a data transform pipeline based on the metadata.

Abstract: Methods and systems may include processes by which the reliability and robustness of a wireless network may be improved. In some implementations, a method may include selecting at least two resource units to be used for communications to a single client device; and transmitting data in duplicate via each of the at least two resource units to the client device such that the client device is able to combine the data from each of the at least two resource units into a single instance of the data. In some implementations, a method may include obtaining notification of one or more ranges of frequencies corresponding to a set of resource units to be avoided in a spectrum of available frequencies, and allocating resource units to a set of client devices that covers the available frequencies while excluding the set of resource units to be avoided.

Abstract: According to an aspect of an embodiment, an optical line terminal (OLT) configured for downstream transmission in a passive optical network (PON) may comprise a processing device and a transceiver. The processing device may be configured to: generate a first downstream signal for transmission on a first channel at a first signal level, and generate a second downstream signal for transmission on a second channel at a second signal level. The first signal level may be greater than the second signal level. The PMD transmitter may be configured to transmit a combined downstream signal comprising the first downstream signal and the second downstream signal. The first transmit power of the first downstream signal may be selected based on a comparison to a second transmit power of the second downstream signal to facilitate reception of the first downstream signal from the combined downstream signal at an optical network unit (ONU).

Abstract: Embodiments are described herein that involve various configurations of UMAC and LMACs in a multi-link operations architecture. Some of these embodiments allow for multi-link operations using multiple different kinds of wired and wireless connections. The embodiments, also describe configurations that allow for the physical separation of UMAC and LMAC components.

Abstract: A method for multi-path interference (MPI) detection and localization may include one or more of: measuring a path delay of a signal; mapping the path delay to a connector-pair distance; or computing a reflection location based on the connector-pair distance. A device may include a processing device operable to perform the method. A system may include a pluggable module and an on-board component.

Abstract: An access point (AP) may include a processing device. The processing device may switch, at the AP, from a primary channel to a non-primary channel access (NPCA) primary channel. The AP may identify, at the AP, one or more stations (STAs) on the NPCA primary channel. The AP may send, from the AP to the one or more STAs on the NPCA primary channel, one or more downlink frames using the NPCA primary channel.

Abstract: A controller may include a voltage regulator, a hysteretic window generator, a phase angle, a phase balance, and a pulse width modulator. The voltage regulator may generate a control signal. The hysteretic window generator may generate, based on the control signal, an upper voltage threshold and a lower voltage threshold. The phase angle may generate phase angle data. The phase balance may receive a total current for multiple phases and generate, based on the total current and the phase angle data, phase balance data. The pulse width modulator may generate, based on the phase balance data, a pulse width modulated signal for a phase of the multiple phases.

Abstract: A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

Abstract: A method includes obtaining an address associated with a data transform command. The address may be disposed in a container located in a first memory. The method also includes obtaining metadata associated with the data transform command. The data transform command may be disposed in the first memory and may be pointed to by the address. A first portion of the metadata may be public data and a second portion of the metadata may be sensitive data. The method further includes storing the public data in the first memory and the sensitive data in a second memory disposed internally to a data transform accelerator. The method also includes configuring a data transform pipeline in the data transform accelerator based on the public data in the first memory and the sensitive data in the second memory.

Abstract: Example methods relate to avoiding beacon collisions between a repeater and a root AP, optimizing traffic flows based on buffers queued within hardware, and/or optimizing transmissions through a trigger-based mechanism. An example method includes determining loads on buffers within a repeater configured to communicate according to a DBVC protocol. The loads on the buffers correspond to data to be transmitted within upstream and downstream networks. The method includes determining whether to adjust a DBVC duty cycle of the repeater based on the loads. The DBVC duty cycle includes: an on channel duty cycle comprising a ratio of time on an on channel to total time on both the on and off channels; or an off channel duty cycle comprising a ratio of time on the off channel to total time on both the on and off channels. The method includes adjusting the DBVC duty cycle of the repeater.

Abstract: Technology is disclosed for a digital signal processor. The digital signal processor may include a first path including a first path-select that may select a first linear path or a first retimed path, and a second path comprising a second path-select that may select a second linear path or a second retimed path.

Abstract: According to an aspect of an embodiment, a decision feedback equalizer (DFE) may be configured for noise suppression slicing. The DFE may be configured to receive, from a feedforward equalizer, an output signal having a received (Rx) symbol. The DFE may be configured to initialize noise suppression slicer (NSS) parameters including one or more initial NSS coefficients and one or more initial slicer deferred decision (SDD) threshold offsets. The DFE may be configured to determine one or more updated NSS coefficients. The DFE may be configured to determine one or more updated SDD threshold offsets. The DFE may be configured to update the NSS parameters of a processing register based on the one or more updated NSS coefficients and the one or more updated SDD threshold offsets.

Abstract: A high-speed serial interface (HSIF) for communicating between an analog front end (AFE) and a radio via a bi-directional serial bit connection for an OFDM device.

Abstract: A calibration system comprises control circuitry and waveform capture circuitry. The control circuitry selects a first calibration waveform for input to a digital predistortion circuit of a transmitter. The capture circuitry captures a first waveform output by the transmitter in response to the first calibration waveform. The control circuitry compares the first calibration waveform to the captured first waveform. The control circuitry selects a first one of a plurality of mapping circuit configurations based on the result of the comparison, wherein the mapping circuit is configured to map outputs of a plurality of delay circuits among inputs of a plurality of filter taps. The control circuitry stores the one of the mapping circuit configurations in nonvolatile memory associated with the transmitter.

Abstract: A wireless network device comprises a wireless signal driver, an application-driver framework that includes a bidirectional interface and an application interface. The application-driver framework is configured for application-agnostic and driver-agnostic communication. The bidirectional interface communicatively couples the wireless signal driver to the application-driver framework. The bidirectional interface includes an abstraction layer via which driver-agnostic command signals and driver-agnostic event signals are communicated with the application-driver framework and via which driver-specific command signals and driver-specific event signals are communicated with the wireless signal driver. The application interface is configured to interface with applications and with the application-driver framework.

Abstract: A cable modem comprises transmitter circuitry, receiver circuitry, and memory. Upon power up of the cable modem in the field, the transmitter circuitry transmits one or more first signals into a network. The receiver circuitry measure echoes of the transmitted one or more first signals. The receiver circuitry generates an installation figure of merit based on the measured echoes and factory-calibration echo measurements stored in the memory. The communication device begins DOCSIS® network registration if the installation quality measurement meets a determined requirement and generates a notification to troubleshoot the installation of the communication device if the installation quality measurement does not meet a determined requirement.

Abstract: A method may include obtaining, by a host device, multiple interrupts from a data transform accelerator. The method may also include determining, by the host device, a first interrupt rate and a second interrupt rate. The method may further include determining, by the host device, an interrupt ratio based on the first interrupt rate relative to the second interrupt rate. The method may also include comparing the interrupt ratio to an interrupt threshold. The method may further include directing, by the host device, the data transform accelerator to adjust an interrupt throttle value associated with the multiple interrupts. The adjusting of the interrupt throttle value may be in response to the interrupt ratio satisfying the interrupt threshold.

Abstract: The present disclosure is directed to time stamp detection using a cable modem and to a control apparatus, control device and control method for detecting timestamps in various signals such as orthogonal frequency division multiplexing (OFDM) signals. The control apparatus comprising processing circuitry being configured to obtain information a channel frequency response of the multi-path channel, the channel frequency response being based on a signal comprising a sequence of symbols. The processing circuitry is configured to transform the channel frequency response into a channel impulse response. The processing circuitry is configured to identify a peak in the channel impulse response. The processing circuitry is configured to determine a timestamp offset time between the peak in the channel impulse response and a trigger time indicative of a beginning of a symbol in the signal. The processing circuitry is configured to synchronize the device clock based on the timestamp offset time.

Abstract: According to an example, a massive multiple-input multiple-output (mMIMO) system operable for beamforming actuation may comprise an open radio access network radio unit (O-RU) having a processing device operable to: compute one or more of a predictive channel estimate, a beamforming estimate, or an antenna calibration; compute, based on an objective function having one or more of the predictive channel estimate, the beamforming estimate, or the antenna calibration as inputs, a power level for a data stream associated with a transmitting antenna path, wherein the power level for the data stream is selected to facilitate an equal-power distribution across a plurality of transmitting antenna paths; and set the power level for the data stream associated with the transmitting antenna path.

Abstract: A system may include an aiming device. The aiming device may include a first transceiver and a second transceiver. The first transceiver may communicate with a remote controlled vehicle (RCV) using free space optics (FSO). The second transceiver may communicate with a controller device using a communication link. The aiming device may direct an FSO communication signal to a first reception cone of the RCV.