Abstract: A diversity receiver includes a first RF front end module for receiving a first RF signal, and frequency converting the first RF signal and outputting a first diversity signal, a second RF front end module for receiving a second RF signal, frequency converting the second RF signal and outputting a second diversity signal, a first converter for converting the first diversity signal to a first time-domain signal, a second converter for converting the second diversity signal to a second time-domain signal, a first transformer for translating the first time-domain signal to a first frequency-domain signal, a second transformer for translating the second time-domain signal to a second frequency-domain signal, a first pre-equalizer for equalizing the first frequency-domain signal, a second pre-equalizer for equalizing the second frequency-domain signal, and a combiner for combining the first and second pre-equalized frequency-domain signals.

Abstract: A multi-service antenna may comprise: a support structure, a reflector mounted to the support structure, a signal processing assembly mounted with the support structure, a first wire strung between the reflector and the support structure and/or the signal processing assembly, and circuitry for processing a first signal received as a result of electromagnetic radiation (e.g., terrestrial television and/or cellular signals) incident on the first wire. The circuitry for processing the first signal may be housed in the signal processing assembly. A second wire may also be strung between the reflector and the support structure and/or the signal processing assembly, and the circuitry may be operable to perform diversity processing of signals received via the two wires.

Abstract: A communication receiver which applies signal processing for quantitatively estimating receive signal factors such as communication channel quality, signal characteristics, and overall system received bit error rate (BER) or packet error rate (PER) and which applies a general algorithm for mapping these estimated factors to control receiver performance and minimize power consumption.

Abstract: A receiver includes a static I/Q calibration block and a correlation/integration block. The static I/Q calibration block is configured to substantially eliminate mismatches between in-phase and quadrature components of a portion of the spectrum having associated I/Q mismatches that are relatively frequency-independent. The correlation/integration block is configured to substantially eliminate mismatches between the in-phase and quadrature components of portions of the spectrum having associated I/Q mismatches that are relatively frequency-dependent in accordance with a pair of signals generated by the static I/C calibration block.

Abstract: To determine the level of frequency drift of a crystal oscillator as a result of a change in the its temperature, the temperature of the crystal oscillator is sensed and used together with previously stored data that includes a multitude of drift values of the frequency of the crystal oscillator each associated with a temperature of the crystal oscillator. Optionally, upon initialization of a GPS receiver in which the crystal oscillator is disposed, an initial temperature of the crystal oscillator is measured and a PLL is set to an initial frequency in association with the initial temperature. When acquisition fails in a region, the ppm region is changed. The temperature of the crystal oscillator is periodically measured and compared with the initial temperature, and the acquisition process is reset if there is a significant change in temperature. The GPS processor enters the tracking phase when acquisition is successful.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: A tuner includes, in part, one or mixers, one or more filters, one or more variable gain stages, one or more analog to digital converters, and a baseband processor. Each filter is responsive to an associated mixer's output signal. Each variable gain stage is responsive to an associated filter's output. Each analog-to-digital converter is adapted to convert the output signal of an associated variable gain stage to a digital signal. The baseband processor is responsive to the digital signal supplied by the analog-to-digital converter(s). The baseband processor is further configured to supply a signal to be demodulated by a processing unit external to the integrated circuit. The baseband processor performs no or a fraction of the required demodulation functions. The processing unit may be a central processing unit or a graphical processing unit.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: A harmonic rejection mixer includes a first scaling circuit for scaling an RF signal to generate a plurality of scaled RF signals, a first switching stage for sampling the scaled RF signals using a first plurality of switching signals, and a second mixing stage for mixing the sampled RF signals with a second plurality of switching signals to generate a plurality of frequency translated signals having different phases. A combiner adds the frequency translated signals together to generate a first plurality of baseband versions of the RF signal. A first amplifier stage processes the first plurality of baseband versions to generate a second plurality of baseband versions. The mixer further includes a second scaling circuit for scaling the second plurality of baseband versions and a second amplifier stage to generate an in-phase baseband signal and a quadrature baseband signal from the scaled second plurality of baseband versions.

Abstract: A circuit for self-calibrating a gain control system samples the output of a digital amplifier coupled in series with one or more analog amplifiers to correct errors in a discrete stepped gain control. A digital gain control circuit controls both the digital amplifier and at least one analog amplifier to produce a smooth linear and continuous gain, wherein perturbations in the digital control of gain are smoothed by a signal applied to gain control circuit by a gain step correction circuit.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: A receiver configured to selectively receive an RF signal from an operating band having a plurality of RF channels. The receiver is configured to upconvert the desired RF channel to an intermediate frequency (IF) greater than the RF channel frequencies. The upconverted RF channel is downconverted to baseband or a low IF. The receiver can perform channel selection by filtering the baseband or low IF signal. The baseband or low IF signal can be upconverted to a programmable output IF.

Abstract: A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware.

Abstract: Erasure information associated with a received group of encoded and interleaved data in a digital video broadcasting system is stored in a much compacted form. An erasure flag and an address of a last byte associated with the received group of encoded and interleaved data (a record) encapsulated in an MPE-FEC column will be stored in an erasure table. All bytes in the column preceding the last byte of the record will have the same erasure flag as the last byte. Erasure information deinterleaver 524 reads out the content of the erasure table (i.e., the erasure information) in a de-interleaving fashion; and the de-interleaved erasure information 525 are then applied with the de-interleaved coded signals 511 to an FEC decoder 526 to enhance the FEC decoding performance.

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

Abstract: A wireless communication receiver includes a multitude of look-up tables each storing a multitude of DC offset values associated with the gains of an amplification stage disposed in the wireless communication receiver. The entries for each look-up table are estimated during a stage of the calibration phase. During such a calibration stage, for each selected gain of an amplification stage, a search logic estimates a current DC offset number and compares it to a previous DC offset estimate that is fed back to the search logic. If the difference between the current and previous estimates is less than a predefined threshold value, the current estimate is treated as being associated with the DC offset of the selected gain of the amplification stage and is stored in the look-up table. This process is repeated for each selected gain of each amplification stage of interest until the look-up tables are populated.

Abstract: A power-saving GNSS includes a sensor for detecting a motion of the receiver, an RF front-end for receiving satellite signals, and a central processing unit coupled to the front-end for acquiring a set of the received satellite signals if the motion is detected. The receiver further include a signal strength evaluator for evaluating a signal strength of the acquired set of the received signals and a counter to count a time period for which the signal strength is below a predetermined value. The receiver also includes a control unit for setting the receiver into an intermittent operating mode if the signal strength exceeds the predetermined value sets the receiver into a power-saving mode if the signal strength is below the predetermined value for the time period determined by the counter. The receiver may also be set into the power-saving mode if it remains stationary for a given time interval.