Abstract: Aspects of the disclosure provide an electronic device including processing circuitry and a method. The processing circuitry can determine whether a collision is scheduled in one of a set of carriers at a same time with an SRS transmission switching process including an SRS transmission scheduled in a current carrier in the set of carriers. The set of carriers is activated for the electronic device. When no collision is determined to be scheduled in the set of carriers at the same time with the SRS transmission switching process, the processing circuitry can determine a SRS interruption duration for a victim carrier to be interrupted by the SRS transmission switching process based on a SRS transmission switching duration, a timing between the SRS transmission switching process and the victim carrier, a numerology of the current carrier, and a numerology of the victim carrier and transmit the SRS transmission.

Abstract: The invention provides method and apparatus augmenting functionality of an antenna-in-module (AiM) of a user equipment (UE) to proximity detection (and more) besides wireless communication. The AiM may comprise a radiator set and a channel circuit set. The radiator set may comprise one or more radiators, and the channel circuit set may comprise one or more channel circuits. The method may comprise: causing a first subset of the channel circuit set to transmit outgoing electromagnetic (EM) waves by circular polarization of a first rotation sense, causing a second subset of the channel circuit set to receive incoming EM waves by circular polarization of a second rotation sense different from the first rotation sense, accordingly obtaining one or more received detection signals, and executing the proximity detection according to the one or more received detection signals.

Abstract: A crystal oscillator (XO) and a method for performing startup of the XO are provided. The XO includes a XO core circuit, an auxiliary oscillator and a frequency detection circuit, wherein the frequency detection circuit includes a resistive circuit. The frequency detection circuit generates a detection voltage according to a driving signal associated with an auxiliary signal generated by the auxiliary oscillator and a first impedance of the resistive circuit. During a first powered on phase, the auxiliary oscillator is calibrated by utilizing the XO core circuit as a reference after startup of the XO core circuit is completed, and the resistive circuit is calibrated according to the detection voltage. During a second powered on phase, a frequency of the driving signal is calibrated according to the detection voltage, and the driving signal is injected to the XO core circuit for accelerating the startup of the XO core circuit.

Abstract: A controller within a mesh network includes at least a station (STA) associated with the controller. The controller is arranged to: set a plurality of received signal strength intensity (RSSI) thresholds respectively corresponding to a plurality of operating bands of the controller, when an RSSI of the STA crosses one of the plurality of set thresholds, performing a calculation to determine respective scores of all enabled links of the STA, according to the calculation, determining a best number of spatial streams (NSS) configuration of the STA, and sending an action frame to the STA for informing the STA to update its NSS configuration.

Abstract: A method for performing channel management in a wireless communication system and associated apparatus are provided. The method may include: receiving, by the first wireless transceiver device, a channel switch request in a first communication frame from the second wireless transceiver device; and triggering a channel switch (CS) mechanism, by the first wireless transceiver device, to inform the second wireless transceiver device to switch from a first channel to a target channel, for subsequent communication of the second wireless transceiver device.

Abstract: The present invention provides a power clamp cell including a power clamping circuit, a power routing and a global routing is disclosed. The power routing has at least a first vertical metal line and a first horizontal metal line, and the power routing is implemented by using a first metal layer in semiconductor process. The ground routing has at least a second vertical metal line and a second horizontal metal line, and the ground routing is implemented by using a second metal layer in the semiconductor process.

Abstract: A controller in a network includes a server and at least a first agent and a second agent, wherein the controller is arranged to, upon an initial boot up of all devices, determine if the first agent and the second agent are onboarding, when it is determined the first agent and the second agent are onboarding, the controller is arranged to wait to receive respective status messages from the first agent and the second agent, consolidate information in the received status messages into a single query, and send the single query to the server.

Abstract: A multi-stage interconnection network includes an M-stage plane routing network and an N-stage destination routing network. The M-stage plane routing network routes a data packet received by an input port of the multi-stage interconnection network to a switch plane according to an M-bit entry selected from a plane encoding table, wherein M bits of the M-bit entry control M stages of the M-stage plane routing network, respectively. The N-stage destination routing network routes the data packet from the switch plane to at least one output port of the multi-stage interconnection network according to at least one N-bit entry selected from a destination encoding table, wherein N bits of each of the at least one N-bit entry control N stages of the N-stage destination routing network, respectively. The multi-stage interconnection network employs a non-blocking network topology.

Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.

Abstract: A method for UE capability signaling for supporting reference signal based measurements in NR-U is proposed. A UE transfers its UE capability information to a mobile communication network, wherein the UE capability information includes information regarding whether the UE supports measurements of a CSI-RS on an unlicensed cell. The UE receives configuration from the mobile communication network, wherein the configuration includes information regarding radio resources of the CSI-RS on the unlicensed cell. The UE measures the CSI-RS on the unlicensed cell based on the configuration.

Abstract: A device is provided, which includes one or more antennas and a circuit. The circuit is configured to receive a packet from a transmitter device through the antennas, and obtain channel-state information from the received packet. The circuit includes one or more filters to filter out or recognize the received packet that complies with one or more preset conditions. The circuit uses the channel-state information of the received packet, which complies with the one or more preset conditions, to estimate a status of a channel between the transmitter device and the device.

Abstract: A chip includes a peripheral component interconnect express (PCIe) switch, a dual-mode device, and a signal transmission control circuit. The PCIe switch includes a first downstream port. The dual-mode device switches between a root complex (RC) mode and an endpoint (EP) mode. The signal transmission control circuit is coupled between the PCIe switch and the dual-mode device. The first downstream port communicates with the dual-mode device operating under the EP mode. The signal transmission control circuit allows an external PCIe device to communicate with the dual-mode device operating under the RC mode.

Abstract: A semiconductor package includes a substrate, a first insulation layer, a conductive via and a conductive trace. The substrate includes a conductive component. The first insulation layer is formed on the substrate and having a first through hole exposing the conductive component. The conductive via is formed within the first through hole. The conductive trace is directly connected to the conductive via which is located directly above the first through hole.

Abstract: Mechanism of relay UE discovery and relay UE selection and reselection for remote UE data transmission with a serving base station via relay UE is proposed. A method operable for relay UE selection and reselection of remote UE is provided. The UE considers additional criteria such as relay load other than purely radio signal quality (e.g., RSRP) criteria. The relay load can serve different purpose for relay UE and remote UE. The relay load can be the criteria for UE to become a relay UE or not. It can be the criteria for a remote UE to select another UE as its relay UE.

Abstract: A method of managing access to a first memory via a second memory includes autonomously copying data from one or more of the data blocks in the first plurality of data blocks in the first memory to corresponding one or more of the data blocks in the second plurality of data blocks in the second memory sequentially. Access to the first memory with a first plurality of data blocks is at a first speed and access to the second memory with a second plurality of data blocks is at a second speed. A command is received for reading from the second memory. Responsive to receiving the command, a pointer is obtained indicating an address of a data block in the second memory that contains data copied from the first memory and that is first available for access. The data is obtained from the data block based on the pointer.

Abstract: A method for determining a State of Charge of a battery module with a first battery having a first rated capacity and a second battery having a second rated capacity including determining an adjusted rated capacity according to at least one of property data of the first battery, property data of the second battery and a system requirement, wherein the adjusted rated capacity is smaller than a summation of the first rated capacity and the second rated capacity; and determining a State of Charge (SoC) which indicates a level of charge of the battery module relative to a total capacity of the battery module according to the level of charge of the battery module and the adjusted rated capacity.

Abstract: The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry includes a write buffer and a negative voltage provider. The write driver is configured to receive input data to drive bit lines of the memory array, and the negative voltage provider is configured to generate to generate a negative voltage to the write driver. The control circuit includes an NBL timing control circuit configured to generate an NBL enable signal to selectively enable the negative voltage provider. In addition, the memory device is supplied by a first supply voltage and a second supply voltage, a voltage level of the second supply voltage is higher than a voltage level of the first supply voltage, and the negative voltage provider and the NBL timing control circuit are supplied by the second supply voltage.

Abstract: The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry is configured to access the memory array. The control circuit is configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry, wherein the IO circuitry is supplied by a first supply voltage, the control circuit is supplied by at least a second supply voltage different from the first supply voltage.

Abstract: The present invention provides a multiplication-accumulation circuit including a switched capacitor module, a buffer and a voltage-to-delay converter. The switched capacitor is controlled by an input signal to receive a ramp signal to generate a voltage signal. The buffer is configured to receive the voltage signal to generate a buffered signal. The voltage-to-delay converter is configured to convert the buffered signal to an output delay signal having delay time information.

Abstract: A signal loss compensation method, for compensating an input signal comprising (K+Y) lost signal units and normal signal units. The signal loss compensation method comprises: compensating 1st to (K?1)th lost signal units by a first signal loss concealment algorithm to generate a first compensation signal and accordingly generating a first synthetic signal; compensating (K+X+1)th to (K+Y) th lost signal units by a second signal loss concealment algorithm to generate a second compensation signal and accordingly generating a second synthetic signal; compensating K th to (K+X)th lost signal units by the first signal loss concealment algorithm or the second signal loss concealment algorithm to generate a third synthetic signal; generating an output signal according to the first synthetic signal, the second synthetic signal, the third synthetic signal and the normal signal units. K and Y are positive integers, X is a natural number, and Y is larger than X.