Patents Assigned to Meiko Electronics Co., Ltd.
  • Patent number: 11128190
    Abstract: A winding electric wire enables a space factor to be increased and an eddy current to be suppressed, despite using an easy winding process. A winding electric wire is configured such that one enameled wire or a plurality of enameled wires bundled in parallel or in a litz form are braided so as to be formed into a belt-like rectangular or square wire shape having flat braided wires forming flatly-molded layers the number that is two or a multiple of two.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: September 21, 2021
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Kimiaki Iwaya, Yuki Kaketa
  • Patent number: 10665568
    Abstract: To provide a technique of preventing, in an encapsulated circuit module having a metal shield layer covering a surface of a resin layer containing filler, the shield layer from falling off. In manufacturing encapsulated circuit modules, first, a substrate 100 is covered with a first resin 400 containing filler together with an electronic component 200. Next, a surface of the first resin 400 is covered with a second resin 500 containing no filler. Subsequently, a ground electrode 110 in the substrate 100 is exposed by snicking and then a shield layer 600 that covers the entire surface of the substrate 100 is formed by electroless plating. Thereafter, snipping is performed to obtain a number of encapsulated circuit modules.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 26, 2020
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventor: Satoru Miwa
  • Patent number: 10537021
    Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film (1) having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film (3) on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film (21) on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: January 14, 2020
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventor: Shigeru Michiwaki
  • Patent number: 10385076
    Abstract: A surface treatment agent including a compound (?) is provided. The compound (?) has one or more M-OH groups and/or groups capable of forming M-OH (wherein M represents a metal atom), an amino group and a triazine ring; wherein said amino group is bonded to a terminal; one or more said amino groups bonded to the terminal are present; and one or more said triazine rings are present.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 20, 2019
    Assignees: Sulfur Chemical Laboratory, Inc., Meiko Electronics Co., Ltd.
    Inventors: Kunio Mori, Yusuke Matsuno, Katsuhito Mori, Takahiro Kudo, Shuukichi Takii, Shigeru Michiwaki, Manabu Miyawaki, Masanori Yanai, Kouichi Kamiyama, Hitomi Chiba, Yasuyuki Masuda
  • Publication number: 20190124763
    Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film (1) having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film (3) on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film (21) on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Applicant: MEIKO ELECTRONICS CO., LTD.
    Inventor: Shigeru MICHIWAKI
  • Patent number: 10244624
    Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: March 26, 2019
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventor: Shigeru Michiwaki
  • Publication number: 20180160528
    Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.
    Type: Application
    Filed: October 30, 2015
    Publication date: June 7, 2018
    Applicant: MEIKO ELECTRONICS CO., LTD.
    Inventor: Shigeru MICHIWAKI
  • Publication number: 20170334933
    Abstract: A surface treatment agent including a compound (?) is provided. The compound (?) has one or more M-OH groups and/or groups capable of forming M-OH (wherein M represents a metal atom), an amino group and a triazine ring; wherein said amino group is bonded to a terminal; one or more said amino groups bonded to the terminal are present; and one or more said triazine rings are present.
    Type: Application
    Filed: August 8, 2017
    Publication date: November 23, 2017
    Applicants: Sulfur Chemical Laboratory, Inc., Meiko Electronics Co., Ltd.
    Inventors: Kunio MORI, Yusuke MATSUNO, Katsuhito MORI, Takahiro KUDO, Shuukichi TAKII, Shigeru MICHIWAKI, Manabu MIYAWAKI, Masanori YANAI, Kouichi KAMIYAMA, Hitomi CHIBA, Yasuyuki MASUDA
  • Patent number: 9793218
    Abstract: In a method for manufacturing a device embedded substrate, a conductive via that penetrates a first insulating layer and a second insulating layer from an outer metal layer to reach a second terminal of an IC device is formed after forming the outer metal layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: October 17, 2017
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Mitsuaki Toda, Tohru Matsumoto, Seiko Murata
  • Patent number: 9756732
    Abstract: A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: September 5, 2017
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Yasuaki Seki, Tomoyuki Nagata, Mitsuaki Toda
  • Patent number: 9622352
    Abstract: In a mark forming step in a manufacturing method for a component incorporated substrate in which an electronic component is positioned with reference to a mark formed in a copper layer, when an imaginary line extending from a search center of a search range of a sensor, to an edge side of the search range is represented as a search reference line and an imaginary line extending, in a state in which a mark center, is matched with the search center, from the mark center in the same direction as the search reference line to an outer ridgeline of the mark is represented as a mark reference line, the mark formed in a shape in which the outer ridgeline of the mark is present in a position where a length of the mark reference line is in a range of 30% or more of the search reference line.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: April 11, 2017
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Ryoichi Shimizu, Mitsuo Iwamoto, Mitsuaki Toda
  • Patent number: 9596765
    Abstract: A manufacturing method for a component incorporated substrate according to the present invention includes positioning an electronic component with reference to a mark formed on a copper layer, the mark consisting of a material less easily etched than copper by a copper etching agent used for etching of copper, after mounting the electronic component on the copper layer with an adhesive layer interposed therebetween, embedding the electronic component and the mark in an insulating substrate, thereafter, etching and removing a part of the copper layer to form a window for exposing the mark, forming an LVH reaching a terminal of the electronic component with reference to the exposed mark, electrically connecting the terminal and the copper layer via a conduction via formed by applying copper plating to the LVH, and, thereafter, forming the copper layer into a wiring pattern.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: March 14, 2017
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Akira Yamaki, Tatsuya Kikuchi, Mitsuaki Toda
  • Patent number: 9593423
    Abstract: The purpose of the present invention is to provide a wiring substrate from which a metal film cannot be detached easily. A process for forming a metal film comprises a step (X) of applying an agent containing a compound (?) onto the surface of a base and a step (Y) of forming a metal film on the surface of the compound (?) by a wet-mode plating technique, wherein the compound (?) is a compound having either an OH group or an OH-generating group, an azide group and a triazine ring per molecule, and the base comprises a polymer.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: March 14, 2017
    Assignees: Sulfur Chemical Laboratory Incorporated, Meiko Electronics Co., Ltd.
    Inventors: Kunio Mori, Yusuke Matsuno, Katsuhito Mori, Takahiro Kudo, Shigeru Michiwaki, Manabu Miyawaki
  • Patent number: 9526182
    Abstract: The method includes positioning an electronic component using main marks formed on a metal layer and mounting the electronic component on a second surface of the metal layer with an adhesive layer interposed between the metal layer and both of the electronic component and terminals; then burying the electronic component and the main marks in an insulating substrate; then removing part of the metal layer and forming a first window for exposing the main marks therefrom and a second window for exposing the adhesive layer including a position corresponding to the terminal therefrom; then using the exposed main marks as references and forming a laser via hole LVH reaching the terminal in the adhesive layer exposed from the second window; and thereby forming a wiring pattern from the metal layer electrically connected to the terminal through a first conductive via formed by plating the LVH with copper.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: December 20, 2016
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Ryoichi Shimizu, Tohru Matsumoto, Takuya Hasegawa, Yoshio Imamura
  • Patent number: 9380711
    Abstract: A substrate manufacturing method includes an inner layer circuit forming step for partially removing metal films from an insulating base material (2), on both surfaces of which the metal films are stuck, and forming an inner layer circuit (3); and an insulating layer forming step for applying first insulating resin (4) to each of both the surfaces of the insulating base material (2) with an inkjet system and forming an insulating layer (5). In the insulating layer forming step, a via hole (6) from which the inner layer circuit (3) is partially exposed is formed simultaneously with the application of the first insulating resin (4). Consequently, a step of separately forming a via hole with a laser or the like is unnecessary, expenses are relatively low, and it is possible to simplify a manufacturing process.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: June 28, 2016
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Shukichi Takii, Noriaki Taneko, Shigeru Michiwaki, Mitsuho Kurosu, Yuichiro Naya
  • Patent number: 9363885
    Abstract: A method of fabricating a heat dissipating board according to the present invention, includes: a substrate intermediate forming step of forming a substrate intermediate with an insulating layer made of an insulating resin material and a conducting layer made of a conductive material formed on the insulating layer; a through hole forming step of forming a through hole having an approximately cylindrical shape, the through hole penetrating through the substrate intermediate; an inserting step of inserting a heat conducting member to be disposed in the through hole, the heat conducting member being made of a metal and having an approximately cylindrical shape; and a plastically deforming step of plastically deforming the heat conducting member to be secured in the through hole. Prior to the inserting step, an annealing step of annealing the heat conducting member is performed.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 7, 2016
    Assignee: Meiko Electronics Co., Ltd.
    Inventors: Noriaki Taneko, Tsuyoshi Takagi, Shukichi Takii
  • Patent number: 9355990
    Abstract: The present invention provides a manufacturing method of a device embedded substrate, including: forming a bonding layer of an insulation material on a metal layer formed on a support plate; and mounting an electric or electronic device on the bonding layer, wherein the device is formed of a device main body and a protruding terminal; the bonding layer includes a first bonding body bonded with the metal layer and a second bonding body bonded with the device; the first bonding body is formed along the outer edge of the device; the second bonding body is formed in an area equal or smaller than the area defined by the outer edge of the terminal; and, in the bonding layer forming step, the second bonding body is formed on the first bonding body after the first bonding body is cured.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 31, 2016
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Tohru Matsumoto, Masaru Ogasawara, Mitsuaki Toda
  • Publication number: 20160143126
    Abstract: A method of fabricating a heat dissipating board according to the present invention, includes: a substrate intermediate forming step of forming a substrate intermediate with an insulating layer made of an insulating resin material and a conducting layer made of a conductive material formed on the insulating layer; a through hole forming step of forming a through hole having an approximately cylindrical shape, the through hole penetrating through the substrate intermediate; an inserting step of inserting a heat conducting member to be disposed in the through hole, the heat conducting member being made of a metal and having an approximately cylindrical shape; and a plastically deforming step of plastically deforming the heat conducting member to be secured in the through hole. Prior to the inserting step, an annealing step of annealing the heat conducting member is performed.
    Type: Application
    Filed: June 12, 2013
    Publication date: May 19, 2016
    Applicant: MEIKO ELECTRONICS CO., LTD.
    Inventors: Noriaki TANEKO, Tsuyoshi TAKAGI, Shukichi TAKII
  • Publication number: 20160118346
    Abstract: A device embedded substrate includes: an insulating layer; a first metal layer and a second metal layer that are formed such that the insulating layer is sandwiched therebetween; a device that is embedded in the insulating layer, and in which a connection terminal non-formation surface where a connection terminal is not formed is located on a side close to the first metal layer; an adhesive layer that is located on the connection terminal non-formation surface of the device; and a conductive via that electrically connects the second metal layer and the connection terminal of the device, wherein an area of the adhesive layer on a surface side in contact with the device is smaller than an area of the connection terminal non-formation surface of the device.
    Type: Application
    Filed: May 20, 2013
    Publication date: April 28, 2016
    Applicant: MEIKO ELECTRONICS CO., LTD.
    Inventors: Mitsuaki Toda, Tohru Matsumoto, Ryoichi Shimizu
  • Patent number: 9326376
    Abstract: A printed wiring board includes: an inner layer structure body containing at least an inner layer insulative base material composed of a glass cloth and resin which covers the glass cloth and not containing a resin insulative base material composed only of resin; outer layer wiring formed on a first face of the inner layer structure body; and a solder resist layer formed on a surface of the outer layer wiring, wherein in the inner layer structure body, an opening part is formed, and the solder resist layer is composed of a first ink part covering at least the outer layer wiring that is formed on a partial region of the first face which corresponds to the opening part and a second ink part interposing both ends of the first ink part and being lower in flexibility than the first ink part.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: April 26, 2016
    Assignee: MEIKO ELECTRONICS CO., LTD.
    Inventors: Akihiro Ishikawa, Toru Yamamoto, Kazuya Inokuchi