Abstract: A wafer holder for holding a semiconductor wafer during a thermal wafer treatment process. The wafer holder includes at least three wafer supports. Each wafer support includes an upright shaft and a plurality of flexible fibers supported by the shaft in positions such that at least some of the fibers engage the semiconductor wafer when the wafer rests on the wafer supports.

Abstract: Production of polycrystalline silicon in a substantially closed-loop process is disclosed. The processes generally include decomposition of trichlorosilane produced from metallurgical grade silicon.

Abstract: Production of polycrystalline silicon in a substantially closed-loop process is disclosed. The processes generally include decomposition of trichlorosilane produced from metallurgical grade silicon.

Abstract: Methods are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.

Abstract: A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.

Abstract: A crystal puller for growing monocrystalline ingots includes a side heater adjacent a crucible for heating the crucible and a melt heat exchanger sized and shaped for surrounding the ingot and disposed adjacent a surface of the melt. The heat exchanger includes a heat source having an area for radiating heat to the melt for controlling heat transfer at the upper surface of the melt. The melt heat exchanger is adapted to reduce heat loss at the exposed upper surface portion. Methods for growing single crystal silicon crystals having desired defect characteristics are disclosed.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: Processing a wafer using a double side grinder having a pair of grinding wheels. Warp data is obtained by a warp measurement device for measuring warp of a wafer as ground by the double side grinder. The warp data is received and a nanotopography of the wafer is predicted based on the received warp data. A grinding parameter is determined based on the predicted nanotopography of the wafer. Operation of the double side grinder is adjusted based on the determined grinding parameter.

Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

Abstract: This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer.

Abstract: Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.

Abstract: A hydrostatic pad for use in holding a semiconductor wafer during grinding of the wafer by grinding wheels. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.

Abstract: Methods for reducing the surface roughness of semiconductor wafers through a combination of rough polishing and thermally annealing the wafer.

Abstract: A support for a semiconductor wafer includes a plate having a support surface for supporting the wafer and a recessed surface spaced from the support surface and spaced from the wafer. A plurality of holes extends from the recessed surface, and the support surface is free of holes to inhibit contamination of the wafer.

Abstract: A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.

Abstract: Processes for purifying silicon tetrafluoride source gas by subjecting the source gas to one or more purification processes including: contacting the silicon tetrafluoride source gas with an ion exchange resin to remove acidic contaminants, contacting the silicon tetrafluoride source gas with a catalyst to remove carbon monoxide, by removal of carbon dioxide by use of an absorption liquid, and by removal of inert compounds by cryogenic distillation; catalysts suitable for removal of carbon monoxide from silicon tetrafluoride source gas and processes for producing such catalysts.

Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water, a hydroxide ion source, and a chelating agent. The process produces silicon wafers substantially free from diffused metal ions.

Abstract: Processing a wafer using a double side grinder having a pair of grinding wheels. Warp data is obtained by a warp measurement device for measuring warp of a wafer as ground by the double side grinder. The warp data is received and a nanotopography of the wafer is predicted based on the received warp data. A grinding parameter is determined based on the predicted nanotopography of the wafer. Operation of the double side grinder is adjusted based on the determined grinding parameter.

Abstract: A method of processing a semiconductor wafer using a double side grinder of the type that holds the wafer in a plane with a pair of grinding wheels and a pair of hydrostatic pads. The method includes measuring a distance between the wafer and at least one sensor and determining wafer nanotopology using the measured distance. The determining includes using a processor to perform a finite element structural analysis of the wafer based on the measured distance.

Abstract: A feed assembly and method of use thereof of the present invention is used for the addition of a high pressure dopant such as arsenic into a silicon melt for CZ growth of semiconductor silicon crystals. The feed assembly includes a vessel-and-valve assembly for holding dopant, and a feed tube assembly, attached to the vessel-and-valve assembly for delivering dopant to a silicon melt. An actuator is connected to the feed tube assembly and a receiving tube for advancing and retracting the feed tube assembly to and from the surface of the silicon melt. A brake assembly is attached to the actuator and the receiving tube for restricting movement of the feed tube assembly and locking the feed tube assembly at a selected position.