Abstract: An operation method of a memory system includes sending, by a controller, a first scanning command to a memory and determining a valley voltage by scanning a plurality of memory cells. The valley voltage is determined according to a count of memory cells corresponding to different threshold voltages in a preset threshold voltage interval, the count of memory cells corresponding to the different threshold voltages being obtained by scanning the plurality of memory cells, the valley voltage being a threshold voltage corresponding to the minimum count of memory cells in the threshold voltage interval. The operation method includes sending, by the controller, a first read command to the memory, the first read command being used for instructing the memory to use the valley voltage as a reference read voltage to read target data. The operation method also includes reading, by the memory, the target data according to the valley voltage.

Abstract: A semiconductor device includes a stack of alternating word line layers and insulating layers. The stack includes a core area, a stair step area, and, optionally, a dummy transition area connecting the core area to the stair step area. The semiconductor device also includes a gate line (GL) trench through the stack extending from the core area through the dummy transition area to the stair step area. The GL trench has a first width within the core area and a second width within the stair step area that is different from the first width. The semiconductor device also includes a first channel structure formed through the stack within the core area, and a stair step contact (SCT) formed through at least a portion of the stack within the stair step area. The SCT connects one of the word line layers of the stack within the stair step area.

Abstract: An example memory device includes a first memory cell string, word lines and processing circuitry. The processing circuitry is configured to apply a first verify bias voltage on a selected word line and apply a first bias voltage on a first word line in a pre-verify stage. The processing circuitry is further configured to apply a second verify voltage on the selected word line, apply a first pass voltage on a second word line, apply a second pass voltage on a third word line, and apply a second bias voltage on the first word line in a verify stage. The second bias voltage is smaller than the first bias voltage. At least one of the first pass voltage and the second pass voltage is larger than the second bias voltage.

Abstract: A memory system package structure and a manufacturing method thereof are disclosed. For example, the memory system package structure can include a memory chip, a memory controller and a distribution layer. The memory chip can include a first surface. The memory controller can be positioned on the first surface. The redistribution layer can be positioned on a side of the memory controller facing away from the memory chip. The memory chip and the memory controller can be electrically connected with the redistribution layer.

Abstract: The embodiments of the present application provide an acceptability check method and check system for newly-added production tools. The check method includes: performing, after obtaining several new tool yield data and several old tool yield data, data analysis on the several new tool yield data and the several old tool yield data, determining whether the several new tool yield data and the several old tool yield data belong to a high yield category or a slightly higher yield category, eliminating the corresponding new tool yield data and old tool yield data if “yes”, and taking the remaining new tool yield data and the remaining old tool yield data respectively as screened new tool yield data and screened old tool yield data; determining, based on the screened new tool yield data and the screened old tool yield data, whether the new production tool is acceptable.

Abstract: A read/write switching circuit and a memory are provided. The read/write switching circuit includes: a first data line (Ldat) connected to a bit line (BL) through a column select module, a first complementary data line (Ldat #) connected to a complementary bit line through the column select module, a second data line (Gdat) and a second complementary data line (Gdat #), and further includes: a read/write switching module (101) configured to transmit data between the first data line and the second data line and transmit data between the first complementary data line (Ldat #) and the second complementary data line (Gdat #) during read and write operations in response to read and write control signals; and an amplification module (102) connected between the first data line (Ldat) and the first complementary data line (Ldat #) and configured to amplify data of the first data line (Ldat) and data of the first complementary data line (Ldat #).

Abstract: A method for forming a staircase structure of 3D memory, including: forming an alternating layer stack on a substrate, forming a plurality of staircase regions where each staircase region has a staircase structure having a first number (M) of steps in a first direction; forming a first mask stack to expose a plurality of the staircase regions; removing (M) of the layer stacks in the exposed staircase regions; forming a second mask stack over the alternating layer stack to expose at least an edge of each of the staircase regions in a second direction; and repetitively, sequentially, removing a portion of (2M) of layer stacks and trimming the second mask stack.

Abstract: Embodiments of a hybrid-bonded semiconductor structure are disclosed. The semiconductor structure comprises a first conductive structure and a second conductive structure in a base dielectric layer. The base dielectric layer has a non-flat top surface. A first top surface of the first conductive structure is non-coplanar with a second top surface of the second conductive structure. The semiconductor structure further comprises an alternating dielectric layer stack comprising a plurality of dielectric layers sequentially disposed on the base dielectric layer, wherein at least two of the plurality of dielectric layers have non-uniform thickness. The semiconductor structure further comprises a first lead wire and a second lead wire formed in the alternating dielectric layer stack and electrically connected to the first conductive structure and the second conductive structure, respectively.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate is provided with a peripheral area and an array area; an insulation layer is formed on the substrate; a first mask layer with a first mask pattern is formed on the insulation layer; the insulation layer is etched by taking the first mask layer as a mask, to form a contact hole in the array area; a first electrode layer is formed; a second mask layer with a second mask pattern is formed, in which the second mask layer is arranged on the first electrode layer; and the first electrode layer and the first mask layer are etched by taking the second mask layer as a mask until the insulation layer in the array area is exposed, in which a remaining portion of the first electrode layer forms a lower electrode layer.

Abstract: A wafer processing method and apparatus, a storage medium and an electronic device are disclosed, relating to the field of integrated circuit (IC) manufacturing and wafer stacking. The wafer processing method includes: partitioning a target wafer into one or more pre-divided areas each having one or more dies; determining area ratings for each pre-divided area based on test data of the dies in each pre-divided area; and feeding the area ratings of the pre-divided areas to a trained classification model to determine a classification category of the target wafer; identifying a second wafer having a same classification category as the target wafer; and stacking the target wafer with the second wafer. This method improves the production yield of stacked ICs.

Abstract: The present disclosure provides a method for manufacturing capacitor array, including: forming, on an upper surface of the substrate, a laminated structure including sacrificial layers and support layers; forming a patterned mask layer on an upper surface of the laminated structure; etching the laminated structure based on the patterned mask layer to form a through hole, wherein after the through hole is formed, the patterned mask layer is retained on the upper surface of the laminated structure, and the through hole penetrates through the patterned mask layer and the laminated structure; forming a first electrode on a sidewall and at a bottom of the through hole; forming, in the patterned mask layer and the laminated structure, and removing the sacrificial layer based on the opening; forming a capacitor dielectric layer on a surface of the first electrode; and forming a second electrode on a surface of the capacitor dielectric layer.

Abstract: A signal transmission circuit and method for testing an integrated circuit (IC) are disclosed. The signal transmission circuit includes: an input circuit, configured to generate a first test signal in response to a first control signal and a clock signal; a transfer chain, including multiple stages of serially-connected transfer circuits, where adjacent transfer circuits in the transfer chain are connected via a through silicon via (TSV), the transfer circuit on one end of the transfer chain is connected to the input circuit, and the multiple stages of transfer circuits transfer the first test signal in stage by stage in response to the clock signal; and multiple signal output ends, where a first test signal input end of each stage of transfer circuit is correspondingly connected to one signal output end. The signal transmission circuit improves the effective utilization rate of a chip in an IC having a TSV test circuit.

Abstract: Implementations of the present disclosure disclose a memory controller and an operation method thereof, and a memory system. The operation method of the memory controller can include a starting step of entering a high-order error correction mode when the data read from a memory block belongs to correctable error correction code data and an error bit count of the memory block is greater than a specific value, a detection step of checking whether an inducement type of the error bit count is charge leakage, and a remedying step of complementarily applying programming pulse signals to the memory block if the inducement type is the charge leakage. The present application reduces the refresh probability of the memory block, reduces the write amplification factor, and thus extends the service life of the memory device.

Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Abstract: The present disclosure provides a method for performing a programming operation on a memory cell connected to a bit line and controlled by a word line. The method includes applying a first programming voltage signal to the word line to program the memory cell into a first state, applying a first voltage to the bit line, performing a verify operation when the memory cell is in a second state, determining a classification of the memory cell based on the verify operation, applying a second voltage to the bit line based on the determined classification, applying a second programming voltage signal to the word line to program the memory cell into the first state, applying a third voltage to the bit line, applying a third programming voltage signal to the word line to program the memory cell into the first state, and applying a fourth voltage to the bit line.

Abstract: A method includes forming a stack of alternating insulating layers and sacrificial layers over a substrate; forming a trench through the stack to uncover the substrate to expose lateral sides of the insulating layers and the sacrificial layers, the trench extending from a core area to a stair step area of the stack; forming a liner to cover the exposed lateral sides; removing the liner in the trenches within a first area of the core area and the stair step area to expose the lateral sides of the sacrificial layers of the stack within the first area; removing the sacrificial layers within the first area; removing the liner in the trenches within a second area of the core area and the stair step area to expose the lateral sides of the sacrificial layers of the stack within the second area; and removing the sacrificial layers within the second area.

Abstract: A memory controller, a memory system and an operation method thereof are provided. The memory controller can be used to control a memory device, and be configured to search, according to the number of erase cycles of the memory block, for a read retry table corresponding to a range to which the number of erase cycles belongs, when reading fails. The read retry table can include a plurality of read bias groups. The memory controller can further be configured to perform read retry operations on the memory block according to the read bias groups in the read retry table. The read retry table corresponding to the range to which the number of erase cycles of the memory block belongs may be found by index searching with the number of erase cycles, based on the retry read voltages in the optimal read bias group that the memory device has had initially.

Abstract: Implementations of the present disclosure disclose a memory controller and a control method thereof, a memory apparatus and a control method thereof, and a memory system and a control method thereof.

Abstract: A semiconductor device includes a stack structure and channel holes penetrating through the stack structure. The stack structure includes alternately stacked dielectric layers and conductive layers, the conductive layers including a top select gate layer. The top select gate layer is provided with a first top select gate isolation structure and a second top select gate isolation structure, and the channel holes are located between the first top select gate isolation structure and the second top select gate isolation structure. The second top select gate isolation structure includes an insulation portion, and the insulation portion is divided into a plurality of second top select gate isolation substructures, so that the critical dimension (CD) of the second top select gate isolation substructure may be matched with the CD of the first top select gate isolation structure.

Abstract: The present disclosure provides a high voltage (HV) switch system for a memory device that includes a first switch configured to transfer a boost voltage during a first time period to a first set of selected word lines or a second set of selected word lines of the memory device; a second switch configured to transfer a target regulated voltage during a second time period to the first set of the selected word lines when programming a first set of memory cells coupled to the first set of the selected word lines; and a third switch configured to transfer the target regulated voltage during the second time period to the second set of the selected word lines that is different from the first set of word lines when programming a second set of memory cells coupled to the second set of the selected word lines.