Abstract: Disclosed herein are an exemplary memory device and methods for programing the memory device. In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor can be configured to perform a first programming to a memory cell of the memory device with a first step voltage value. The processor is further configured to determine that a step voltage increase condition is met. The processor can also be configured to perform a second programming to the memory cell of the memory device with the second step voltage value. The second step voltage value is greater than the first step voltage value by an incremental voltage value.

Abstract: A ferroelectric memory cell includes a transistor pair having a first source region, a second source region, a first gate structure, a second gate structure, a first drain region, and a second drain region, a first ferroelectric capacitor formed on and electrically connected to the first drain region, a first plateline formed on and electrically connected to the first ferroelectric capacitor, and a second ferroelectric capacitor formed on and electrically connected to the first plateline. The second ferroelectric capacitor is electrically connected to the second drain region.

Abstract: Aspects of the disclosure provide a method of tilting characterization. The method includes measuring a first tilting shift of structures based on a first disposition of the structures. The structures are formed in a vertical direction on a horizontal plane of a product. A second tilting shift of the structures is measured based on a second disposition of the structures. The second disposition is a horizontal flip of the first disposition. A corrected tilting shift is determined based on the first tilting shift and the second tilting shift.

Abstract: In once example, a memory system includes a controller and a three-dimensional non-volatile memory that are coupled. The three-dimensional non-volatile memory includes a three-dimensional memory array. The three-dimensional memory array includes a plurality of word lines and a plurality of pages that are coupled. The controller is configured to: calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain first RAID parity data, and store the first RAID parity data in a parity buffer space; and calculate received page data corresponding to an (i+1)th word line and ith RAID parity data to obtain (i+1)th RAID parity data, and store the (i+1)th RAID parity data in the parity buffer space, the (i+1)th RAID parity data overwriting the ith RAID parity data, i being a positive integer greater than or equal to 1.

Abstract: A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate including a plurality of pads spaced apart from each other, a first groove, and a second groove connected with the first groove, the first and the second grooves located in the substrate. The first groove is located on the side of the second groove away from the plurality of pads, and the bottom of the second groove exposes a corresponding pad of the plurality of pads. The orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate. A redistribution layer is disposed on a surface of the corresponding pad, the inner wall of the first groove, and the inner wall and the bottom of the second groove. The semiconductor structure prevents contamination or damage of test probes.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.

Abstract: A method for controlling a memory system is disclosed. For example, the method can include performing an operation on a memory device of the memory system, calculating a remaining payload based on a current total payload and a payload associated with the operation performed on the memory device, and when the remaining payload meets a predefined requirement, measuring a current temperature of the memory device and setting the current total payload associated with the current temperature for the memory device.

Abstract: A semiconductor structure and a manufacturing method thereof are present. The method includes: forming a first mask layer having an etching window, wherein the first mask layer includes a first mask sublayer formed on the upper surface of bit line structures, and a second mask sublayer located on the upper surface of the first mask sublayer and the upper surface of an inter-layer dielectric layer, the first mask sublayer has the upper surface level with the upper surface of an inter-layer dielectric layer, and has a plurality of strip-shaped patterns extending in a first direction and spaced apart from each other, and the second mask sublayer has a plurality of strip-shaped patterns extending in a second direction and spaced apart from each other; and etching the inter-layer dielectric layer by using the first mask layer as a mask to form a contact hole exposing a surface of a substrate.

Abstract: The present disclosure describes flash controller for reading data from a flash memory device. A flash memory controller can include a controller storage and one or more processors. The one or more processors are configured to: receive a request for data stored in flash memory dies. The request includes a logical address of the data and at least one flash memory die of the flash memory dies includes one or more on-die static random access memory (SRAM) storage devices. The one or more processors are further configured to: identify an on-die SRAM storage device containing logical-to-physical (L2P) information; search the L2P information to obtain a physical address of the data that corresponds to the logical address; and retrieve the data from a flash memory array of corresponding flash memory die using the physical address.

Abstract: A method for testing a semiconductor device comprises obtaining an alignment signal between one or more auxiliary pins of a test probe and one or more auxiliary pads of a test key of the semiconductor device before a probing test of the semiconductor device. The obtaining of the alignment signal comprises: performing a vertical alignment between the one or more auxiliary pins of the test probe and the one or more auxiliary pads of the test key; and gradually reducing a vertical distance between the one or more auxiliary pins of the test probe and the one or more auxiliary pads of the test key for bringing into an electrical contact until the alignment signal there-between satisfies an alignment condition.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

Abstract: The present disclosure provides a memory device, comprising a memory array having memory cells, a page buffer coupled to the memory array through bit lines. The page buffer comprises a latch, and a control logic coupled to the page buffer and configured to: perform a first read operation on the memory cells; select, from the memory cells, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state, based on the first read operation; perform a second read operation on the first plurality of memory cells; select, from the first plurality of memory cells, a third plurality of memory cells based on the second read operation; perform a third read operation on the third plurality of memory cells; and determine a read develop time based on the third read operation.

Abstract: Embodiments provide a method and apparatus for capacitor demand evaluation in a PDN that includes at least one power bus provided with multiple nodes. The multiple nodes are distributed at different positions of the power bus. Each of the multiple nodes is connected to multiple capacitors connected in parallel. Each of the multiple capacitors is provided with a respective one of control switches. The method includes: Multiple adjustment operations are performed. Upon accomplishment of each of the multiple adjustment operations, a respective IR drop of the power bus and a respective running speed of the load circuit are detected; for each of different nodes on the power bus, an ideal capacitance of the node is determined according to the IR drops of the power bus and running speeds of the load circuit detected through the multiple adjustment operations.

Abstract: The present invention provides a power control circuit and control method. The power control circuit includes: a control module configured to control, according to an activation command, a memory bank of a plurality of memory banks to perform an operation; a power management module configured to wake up a local power supply for the memory bank according to a clock enable signal; and a power control module communicatively coupled with the power management module and configured to: send the clock enable signal to the power management module of the memory bank corresponding to the activation command in a power-saving mode; and send the clock enable signal to power management modules of the plurality of memory banks in a non-power-saving mode, where the power-saving mode indicates that a system clock is in a low-frequency state.

Abstract: The present disclosure provides a memory device, comprising a memory array having memory cells, a page buffer coupled to the memory array through bit lines. The page buffer comprises a latch, and a control logic coupled to the page buffer and configured to: perform a first read operation on the memory cells; select, from the memory cells, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state, based on the first read operation; perform a second read operation on the first plurality of memory cells; select, from the first plurality of memory cells, a third plurality of memory cells based on the second read operation; perform a third read operation on the third plurality of memory cells; and determine a read develop time based on the third read operation.

Abstract: The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.

Abstract: A method for forming a 3D memory device is disclosed. The method includes forming an alternating dielectric stack on a substrate. Then a plurality of channel structures and dummy channel structures vertically penetrating the alternating dielectric stack are formed, The channel structures are located in a core region, and the dummy channel structures are located in a staircase region. A gate line silt structure is formed vertically penetrating the alternating dielectric stack and laterally extending in a first direction. The gate line silt structure includes a narrow portion that has a reduced width along a second direction different from the first direction.

Abstract: The present disclosure provides a method of processing a semiconductor device having a stack formed over a source sacrificial layer above a substrate, a channel structure extending vertically through the stack and the source sacrificial layer, a gate line cut trench extending vertically through the stack, and a spacer layer covering uncovered top and side surfaces of the stack. The method can include exposing a lower sidewall of the channel structure by removing the source sacrificial layer, forming a protection layer on all uncovered surfaces, exposing a channel layer of the channel structure by removing a first portion of the protection layer and an insulating layer of the channel structure, forming an initial source connection layer over the exposed channel layer, exposing the substrate by removing a second portion of the protection layer, and forming a source connection layer over the initial source connection layer and the exposed substrate.

Abstract: Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the method for forming the 3D memory device includes forming an alternating dielectric stack on a substrate, and forming channel holes that penetrate the alternating dielectric stack and expose at least a portion of the substrate. The method further includes forming top select gate openings that penetrate vertically an upper portion of the alternating dielectric stack and extend laterally. The method also includes forming slit openings parallel to the top select gate openings, wherein the slit openings penetrate vertically the alternating dielectric stack. The method also includes replacing the alternating dielectric stack with a film stack of alternating conductive and dielectric layers, forming top select gate cuts in the top select gate openings, and forming slit structures in the slit openings.

Abstract: Aspects of the disclosure provide a semiconductor device and method. An example method include forming a stack of layers on a substrate, the stack of layers including a source sacrificial layer, a conductive layer, gate sacrificial layers and insulating layers; forming a staircase into the stack of layers in a staircase region that is adjacent to an array region; forming channel structures in the array region, a channel structure including a channel layer surrounded by one or more insulating layers and extending into the stack of layers; replacing the source sacrificial layer with a source layer in conductive connection with the channel layer, the source layer and the conductive layer forming a common source layer; replacing the gate sacrificial layers with gate layers; and forming a first contact structure in the staircase region, the first contact structure forming a conductive connection with the common source layer.