Abstract: Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.

Abstract: Object recognition and classification based on data from multiple sensor modalities is disclosed. A computing system can detect an event in a monitored portion of an environment coordinate field associated with a vehicle. The computing system can retrieve data associated with the detected event from a plurality of modalities. At least one of the modalities can include raw data from a sensor associated with the vehicle. The computing system can classify the detected event based at least in part on the retrieved data and one or more parameters of a classifier.

Abstract: Determining a situational annotation of a vehicle based on an annotated environmental model is disclosed. A computing system receives an annotated environmental model for a vehicle. The annotated environmental model can include data from a plurality of modalities. The computing system uses a classifier to determine an annotation of the vehicle situation based, at least in part, on the annotated environmental model. The computing system provides the situational annotation to a driving functionality system. The driving functionality system is configured to use the situational annotation to generate signals to control operation the vehicle.

Abstract: This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can correlate transactions captured during simulation of a circuit design to distributed states for multiple components in the circuit design. The computing system can identify at least a portion of the distributed states for the multiple components correspond to system level coverage events. The computing system can generate a graphical presentation to illustrate the portion of the distributed states for the multiple components in the circuit design that correspond to system level coverage events.

Abstract: This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can identify multiple components in the circuit design to combine for distributed state coverage analysis based, at least in part, on data transactions generated during the simulation of the circuit design. The computing system can correlate information captured during simulation that corresponds to the identified components. The correlated information can identify at least one distributed state coverage event for the test bench. The computing system can generate a distributed state coverage metric based on the correlated information corresponding to the identified components. The computing system can prompt presentation of the correlated information a display window, which can graphically show how a test bench exercised the identified components during simulation.

Abstract: Aspects of the disclosed technology relate to techniques for modeling memories in emulation. An emulator is configured to implement an emulation model for a circuit design and a cache memory model for a memory accessible by the circuit design. A workstation coupled to the emulator is configured to implement a main memory model for the memory. The cache memory model is a hardware model while the main memory model is a software model. The cache memory model stores a subset of data that are stored in the main memory model and is synchronized with the main memory model.

Abstract: This application discloses a computing system configured to simulate an embedded system including a processor capable of executing embedded software, compile the embedded software into a format capable of execution by the computing system, insert instrumentation code into the compiled embedded software, and execute the compiled embedded software and the instrumentation code. The execution of the compiled embedded software can simulate execution of the embedded software by the processor in the simulated embedded system, while the execution of the instrumentation code can configure the computing system to gather information corresponding to the execution of the compiled embedded software.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Abstract: User interface (UI) techniques, and more particularly to graphical user interface (GUI) techniques providing 3-dimensional (3-D) renditions. A method of displaying one or more graphical objects, the method being carried out in an electronic device, the device having processing circuitry, memory and a display device, the method comprising: obtaining first image data defining at least one two-dimensional graphical component; performing a transformation operation on the first image data to generate second image data defining, for the or each graphical component, a modified form of the graphical component; using said second image data, displaying the modified form whereby the or each graphical component has the appearance of having a component of dimension perpendicular to the plane of the display device. Disclosed GUIs can be employed by users to interact with electronic devices having a display, in particular but not limited to hand-held devices with small screens.

Abstract: Embodiments of the disclosed technology comprise a cloud-hosted central service platform that interfaces and enables access to both central and distributed resources and peripherals for connected mobile applications. For example, this platform allows service providers and application developers to create a large number of new classes of applications, leveraging web access to devices, sensors, and/or actuators of any kind. This platform can be applied to virtually any vertical segment. Any of the disclosed features or aspects of the disclosed embodiments can be used in various combinations and subcombinations with one another or with other methods, apparatus, and systems.

Abstract: Technologies for debugging hardware errors discovered during hardware assisted software verification processes are provided. For example, in one embodiment, a concurrent emulation debug environment including a concurrent emulation system, an emulation trace module and a model state module is provided. The concurrent emulation system includes an emulator and an emulation control station configured to allow simultaneous emulation of multiple electronic designs. The model state module is configured to record the state of the electronic designs during emulation and the emulation trace module is configured to capture trace data associated with the emulation. A backup and capture module is also disclosed that is configured to store the recorded state and the captured trace data for use during a hardware debug process.

Abstract: This application discloses a computing system implementing tools and mechanisms to import a three-dimensional mechanical model from a mechanical design system. The three-dimensional mechanical model includes a folded representation of a substrate having a surface for placement of electronic components and electrical connections. The tools and mechanisms can identify one or more bends in the surface of the folded representation of the substrate, and generate a two-dimensional layout representation of the substrate for an electronic design system based, at least in part, on the one or more bends in the surface of the folded representation of the substrate.

Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Abstract: Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.

Abstract: A set of original model candidates are first divided into groups of original model candidates. Child model candidates are generated by performing crossover on each of the groups of original model candidates without mutation. From the original model candidates and the child model candidates, a set of new model candidates are derived, which includes: selecting a group of new model candidates from each group of the original model candidates and the corresponding child model candidates, selecting an additional new model candidate if adding the additional new model candidate increases overall diversity, and performing niche clearing to keep a number of the new model candidates in each of niches from exceeding a maximum number. The dividing, generating and deriving operations are then iterated. Model caching may be performed by restricting the crossover to the model term level or above.

Abstract: Disclosed herein are example embodiments of methods, apparatus, and systems for transactors configured for use in a hardware emulation environment and designed to adapt to speed changes dynamically at runtime in addition to providing dynamic port mapping. Among the embodiments disclosed herein is an emulation system comprising one or more configurable hardware components (e.g., configurable logic blocks) configured to implement a mutable port group transactor in communication with a design under test being emulated by the emulation system. The emulation system can further comprise a host computer in communication with the emulator and configured to provide configuration commands to the emulator that alter the mutable port group transactor from a first configuration to a second configuration.

Abstract: Aspects of the disclosed technology relate to techniques of inserting stress-enhancing filler cells for leakage reduction. Stress analysis is first performed to identify devices with large leakage current in a layout design. An optimization zone in a row of cells that contains one or more of the devices with large leakage current is then determined. Stress-enhancing filler cells are inserted into the optimization zone to replace some or all of the one or more filler cells while placement of the cells in the optimization zone is adjusted based on a leakage reduction analysis.

Abstract: Aspects of the disclosed technology relate to techniques of optical proximity correction for directed self-assembly guiding patterns. An initial mask pattern for photomask fabrication is first generated by performing a plurality of conventional optical proximity correction iterations. Predicted print errors for two or more via-type features are then determined based on a predicted guiding pattern for the two or more via-type features, a target guiding pattern for the two or more via-type features, and correlation information between a plurality of guiding pattern parameters and location and size parameters for the two or more via-type features. Here the predicted guiding pattern is derived based on the initial mask pattern. Based on the predicted print errors and the correlation information, the initial mask pattern is adjusted to generate a new mask pattern.

Abstract: This application discloses a system implementing tools and mechanisms to generate a structured bill of materials for a wire harness described in a harness design, identify variable parameter corresponding to a physical characteristic for a first sub-assembly in the structured bill of materials for the wire harness, and substitute the first sub-assembly in the structured bill of materials for the wire harness with a second sub-assembly based, at least in part, on the variable parameter for the first sub-assembly.