Abstract: Various aspects of the disclosed technology relate to circuit defect diagnosis based on sink cell fault models. Defect candidates are determined based on path-tracing from failing bits into the circuit design. Based on the defect candidates and one or more conventional fault models, failing test pattern simulations are performed to determine initial defect suspects. Initial defective sink cell suspects are then determined by comparing driving strengths for fan-out cells of the initial defect suspects with driving strengths for corresponding driver cells. Defective sink cell suspects may be identified in the initial defective sink cell suspects based on fault effect propagations and passing test pattern simulations.

Abstract: This application discloses a computing system to perform a fast evaluation of a worst case eye diagram for a channel capable of communicating signals encoding data in more than two value levels. The computing system can identify multiple step responses of the channel, each corresponding to a transition between a plurality of the value levels. The computing system can determine distribution boundaries of the signals at each of the value levels based, at least in part, on the step responses of the channel. The computing system can utilize the distribution boundaries at the value levels to determine boundaries of eye openings between adjacent value levels or to build worst case input patterns used to generate the worst case eye diagram for the channel. The computing system can predict a signal integrity of the channel based on the distribution boundaries at each of the value levels.

Abstract: Methods and apparatuses for bounding the processing domain in a symmetric multiprocessing system are provided. In various implementations, a particular computational task is “affined” to a particular processing unit. Subsequently, when the particular task is executed, the symmetric multiprocessing operating system ensures that the affined processing unit processes the instruction. When the affined processing unit is not processing the particular computational task, the symmetric multiprocessing operating system may cause the processing unit to process alternate instructions. With some implementations, a particular computational task is “linked” to a particular processing unit. Subsequently, when the particular task is executed, the symmetric multiprocessing operating system ensures that the bound processing unit processes the instruction. When the bound processing unit is not processing the particular computational instruction, the bound processing unit may enter a low power or idle state.

Abstract: This application discloses a computing system to receive electromigration design rules defining characteristics of integrated circuits configured to cause electromigration, generate a rules library including machine code implementing electromigration design rule checks for the characteristics defined by the electromigration design rules, and perform the electromigration design rule checks on a layout design of an integrated circuit by executing the machine code implementing the electromigration design rule checks on structures of the integrated circuit described in the layout design.

Abstract: Aspects of the disclosed technology relate to techniques of voltage-based reliability verification. Voltage values on nets of a circuit design are determined based on a combination of propagating voltage values across components of the circuit design and simulating one or more subcircuits. The one or more subcircuits are identified based on circuit topology recognition. The determined voltage values are analyzed to detect problems in the circuit design.

Abstract: Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.

Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.

Abstract: Yield excursions in the manufacturing process today require an expensive, long and tedious physical failure analysis process to identify the root cause. Techniques are disclosed herein for efficiently identifying the root-cause of a manufacturing yield excursion by analyzing fail data collected from the production test environment. In particular, statistical hypothesis testing is used in a novel way to analyze logic diagnosis data along with information on physical features in the design layout and reliably identify the cause of the yield excursion.

Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.

Abstract: An event management structure for an embedded system, which supports multiple waiters waiting on the same event without replicating the events for each waiter, is provided. Notifications of events are received from entities within an embedded system. The event management architecture then posts the events to a central queue and generates a unique identification tag for each posted event. Additionally, entities within the embedded system are allowed to wait on specific events. More specifically, entities may request access to specific events based on the unique identification tag associated with a particular event. In further implementations, data associated with queued events may be provided to the waiters. In some implementations, events matching a specific description since a particular event, identified by its unique identification tag, may be requested by entities in the embedded system.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.

Abstract: This application discloses a computing system implementing a source application to extract coverage data from a source database with application program interface (API) routines specific to the source database, and classify the coverage data according to a Unified Coverage Interoperability Standard (UCIS)-compliant format. The coverage data can include at least one of data from verification operations performed on a circuit design, test information utilized during the verification operations, or at least one test plan. The computing system implementing the source application can, based on the classification, select exchange routines to transfer the coverage data towards a target database. The computing system can implement a target application to utilize the classification of the coverage data to identify corresponding API routines specific to the target database, and write the coverage data to the target database with the identified API routines.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for analyzing and/or transforming code (typically, source code) to reduce or avoid redundant or unnecessary power usage (e.g., power cycling, resource leak bugs, and/or unnecessarily repeated activity) in the device that will ultimately execute the application defined by the source code. The disclosed methods can be implemented by a software tool (e.g., a static program analysis tool or EDA analysis tool) that analyzes and/or transforms source code for a software application to help improve the performance of the software application on the target device. The disclosed methods, apparatus, and systems should not be construed as limiting in any way.

Abstract: This application discloses a computing system implementing tools and mechanisms to synchronize multiple layouts for a circuit design during the layout process. The tools and mechanisms can implement multiple communicating kernels, each to manage at least one of the layouts. In response to an alteration of one of the layouts, the kernels can communicate with each other, so that the kernel corresponding to the unaltered layout can automatically augment corresponding layouts for the circuit design to synchronize with the altered layout. At least one of the layouts can include a 3-dimensional layout representation of the circuit design, the tools and mechanisms can perform 3-dimensional design rule checking based on mechanical constraints and 3-dimensional solid component models in response to alterations to a 2-dimensional layout representation of the circuit design.

Abstract: Aspects of the disclosed technology relate to low power testing. A low power test circuit comprises a test stimulus source, a controller; and a grouping and selection unit. The grouping and selection unit has inputs coupled to the test stimulus source and the controller and has outputs coupled to a plurality of scan chains. The grouping and selection unit is configured to dynamically group scan chains in the plurality of scan chains into a plurality of scan chain groups and to selectively output either original test pattern values generated by the test stimulus source or a constant value to each scan chain group in the plurality of scan chain groups based on control signals received from the controller.

Abstract: The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: A system and method is disclosed in an emulation environment that dynamically remaps user designs. In one embodiment, a request is received to load an integrated circuit design to be emulated in a desired partition within the emulator. The emulator automatically determines the availability of the partition requested. If the partition is not available, the design is dynamically remapped to a different partition that is available. In another embodiment, clocks associated with the integrated circuit design are also dynamically remapped. In yet another embodiment, the user can control the size of the partitions (e.g., the number of printed circuit boards in a partition).

Abstract: When a designer designates one or more errors identified in layout design data as false errors, waiver geometric elements corresponding to the designated false errors are created and added to the design. The waiver geometric element may be associated with a verification rule that generated its corresponding false error. When the design is subsequently analyzed using those verification rules in another verification rule check process, the waiver geometric elements are examined, and used to mask those errors associated with a waiver geometric element that would otherwise be displayed to the designer. A designer may also designate a waiver region based on pattern matching, cell names or layout markers in which layout region one or more verification rules may be inapplicable. A waiver region identification item for the waiver region may be associated with a waiver geometric element and the one or more verification rules.

Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.