Patents Assigned to Mentor Graphics
  • Selective Parasitic Extraction
    Publication number: 20150186591
    Abstract: This application discloses a computing system to pre-process a physical or geometric layout of a circuit design to determine various attributes of the nets, such as a location and a total capacitance for each net in the geometric layout. The computing system can order extraction of the nets from the geometric layout of the circuit design with a space filling curve based, at least in part, on the locations of the nets in the geometric layout of the circuit design and any coupling capacitance between the nets in the geometric layout of the circuit design. The computing system can selectively decouple nets with a coupling capacitance based, at least in part, on the total capacitance for the nets associated with the coupling capacitance. The computing system can generate an electrical representation for each of the extracted nets and write them to a netlist for the circuit design.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Applicant: Mentor Graphics Corporation
    Inventors: David J. Gurney, Sandeep Koranne, Mingchao Wang
  • Faulty chains identification without masking chain patterns
    Patent number: 9057762
    Abstract: Aspects of the invention relate to techniques for cycle-based scan chain diagnosis for integrated circuits with embedded compactors. With various implementations of the invention, no-failing-bits output channels of a compactor are first identified based on output data of a test. Next, good scan chains are identified based on scan chains associated with the no-failing-bits output channels. From scan chains other than the good scan chains, analysis of bits outputted from failing-bits output channels per clock cycle is performed to identify suspected faulty scan chains.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: June 16, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Manish Sharma
  • HIGH-FREQUENCY VLSI INTERCONNECT AND INTENTIONAL INDUCTOR IMPEDANCE EXTRACTION IN THE PRESENCE OF A MULTI-LAYER CONDUCTIVE SUBSTRATE
    Publication number: 20150161324
    Abstract: Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.
    Type: Application
    Filed: December 8, 2014
    Publication date: June 11, 2015
    Applicant: Mentor Graphics Corporation
    Inventor: Roberto Suaya
  • Characteristic response extraction for non-linear transmit channels
    Patent number: 9048941
    Abstract: Techniques for extracting the characteristic response of a non-linear channel are presented. In various implementations of the invention, a channel's characteristic response may be determined by identifying a first input sequence, determining the ones compliment of the first input sequence and then determining the response of the channel to these two input sequences. Subsequently, two input matrices and two response matrices may be generated based upon the two input sequences and their corresponding responses. Given these four matrices, a symmetrical response component may be determined by iteratively solving a system of equations formed from the columns of each matrix. Subsequently, given the symmetric component and these four matrices, an asymmetrical response component may be determined by again iteratively solving the system of equations for the columns of each matrix.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: June 2, 2015
    Assignee: Mentor Graphics Corporation
    Inventor: Vladimir B. Dmitriev-Zdorov
  • Clustering for processing of circuit design data
    Patent number: 9047434
    Abstract: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: June 2, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Manjit Borah, Ruiming Chen, Prasanna Srinivas, Prashant Varshney, Amit Jalota, Kirk Schlotman
  • DETERMINATION OF ELECTROMIGRATION SUSCEPTIBILITY BASED ON HYDROSTATIC STRESS ANALYSIS
    Publication number: 20150143318
    Abstract: Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 21, 2015
    Applicant: Mentor Graphics Corporation
    Inventors: Patrick Gibson, Valeriy Sukharev, William Matthew Hogan, Sridhar Srinivasan
  • Grouping Layout Features For Directed Self Assembly
    Publication number: 20150143313
    Abstract: Aspects of the invention relate to techniques of grouping layout features for directed self-assembly (DSA). Via-type features in a layout design are separated into via-type feature groups and isolated via-type features. The derived via-type feature groups are analyzed to determine whether the via-type feature groups are DSA-compliant. The layout design may be modified if one or more via-type feature groups in the via-type feature groups are non-DSA-compliant.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Mentor Graphics Corporation
    Inventor: Juan Andres Torres Robles
  • Determination Of Electromigration Features
    Publication number: 20150143317
    Abstract: For one or more geometric elements partitioned into a plurality of geometric element portions, the expected current directions through each geometric element portion are determined. Using the expected current directions, each expected current path through the geometric element portions is determined. Based upon the expected current paths, and the physical characteristics represented by the geometric element portions in those expected current paths, the electromigration features corresponding to the geometric element or elements are determined. For example, the length of the longest expected current path through the geometric element or elements can be identified based upon the lengths of the geometric element portions and the directions of their currents, and this length can then be compared with the Blech length for the geometric element or elements.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: Mentor Graphics Corporation
    Inventors: Patrick Gibson, Sridhar Srinivasan, William Matthew Hogan
  • Generating guiding patterns for directed self-assembly
    Patent number: 9032357
    Abstract: Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 12, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Juan Andres Torres Robles, Yuri Granik, Kyohei Sakajiri
  • Fault support in an emulation environment
    Patent number: 9026423
    Abstract: An emulator is disclosed that allows for diagnoses of failures or defects within the emulator. A map of faulty resources is generated to identify which resources should be avoided during compilation. Thus, in a transparent and automated manner, defects found during diagnostics are stored in a database of unusable emulator resources. A compiler has access to the database and compiles the design taking into account unusable resources. In another embodiment, the defects of an emulator board are stored on the emulator board itself. This allows each board to store its own maintenance information that can be used at the manufacturing site for changing defective chips. Defects stored on the board itself allow the defects to be obtained independent of a position of a board within the emulator to simplify identification of the faulty resource.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: May 5, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Eric Durand, Estelle Reymond, John Fadel
  • Test access mechanism for diagnosis based on partitioning scan chains
    Patent number: 9026874
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for partitioning-based Test Access Mechanisms (TAM). Test response data are captured by scan cells of a plurality scan chains in a circuit under test and are compared with test response data expected for a good CUT to generate check values. Based on the check values, partition pass/fail signals are generated by partitioning scheme generators. Each of the partitioning scheme generators is configured to generate one of the partition pass/fail signals for one of partitioning schemes. A partitioning scheme divides the scan cells into a set of non-overlapping partitions. Based on the partition pass/fail signals, a failure diagnosis process may be performed.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: May 5, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Wu-Tung Cheng, Manish Sharma, Avijit Dutta, Robert Brady Benware, Mark A. Kassab
  • Diagnosis-aware scan chain stitching
    Patent number: 9015543
    Abstract: Aspects of the invention relate to techniques for determining scan chains that could be diagnosed with high resolution. A circuit design and the information of scan cells for the circuit design are analyzed to determine information of potential logic relationship between the scan cells. The information of potential logic relationship between the scan cells may comprise information of fan-in cones for the scan cells. Based at least in part on the information of potential logic relationship between the scan cells, scan chains may be formed. The formation of scan chains may be further based on layout information of the circuit design. The formation of scan chains may be further based on compactor information of the circuit design.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: April 21, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai
  • Dynamic printed circuit board design reuse
    Patent number: 9015647
    Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: April 21, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Gerald Suiter, Henry Potts
  • Scan chain configuration for test-per-clock based on circuit topology
    Patent number: 9009553
    Abstract: Aspects of the invention relate to generating scan chain configurations for test-per-clock based on circuit topology. With various implementations of the invention, weight vectors between scan chains in a circuit are first determined. Based on the weight vectors, a scan chain configuration is generated by assigning some scan chains in the scan chains to a stimuli group and some other scan chains in the scan chains to a compacting group. Here, the stimuli group comprises scan chains to operate in a shifting-launching mode, and the compacting group comprises scan chains to operate in a capturing-compacting-shifting mode.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 14, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Density-based integrated circuit design adjustment
    Patent number: 9009643
    Abstract: The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: April 14, 2015
    Assignee: Mentor Graphics Corporation
    Inventor: Yuri Granik
  • Adaptive Clock Management In Emulation
    Publication number: 20150100931
    Abstract: Aspects of the invention relate to techniques for adaptive clock management in emulation. A clock suspension request signal, indicating when a suspension of design clock signals in an emulator is needed, is generated based on activity status information of the emulator with one or more emulator resources such as software environment. A clock suspension allowance signal, indicating whether a suspension of design clock signals is permitted considering dynamic targets in the emulator, is generated based on slack information related to one or more clock signals associated with one or more dynamic targets of the emulator. Based on the clock suspension request signal and the clock suspension allowance signal, a clock suspension signal is generated for enabling temporary design clock suspensions.
    Type: Application
    Filed: November 22, 2013
    Publication date: April 9, 2015
    Applicant: Mentor Graphics Corporation
    Inventors: Krishnamurthy Suresh, Charles W. Selvidge, Sanjay Gupta, Amit Jain, Satish Kumar Agarwal
  • Fault-driven scan chain configuration for test-per-clock
    Patent number: 9003248
    Abstract: Aspects of the invention relate to using fault-driven techniques to generate scan chain configurations for test-per-clock. A plurality of test cubes that detect a plurality of faults are first generated. Scan chains for loading specified bits of the test cubes are then assigned to a stimuli group. From the plurality of test cubes, a test cube that detects a large number of faults that do not propagate exclusively to scan chains in the stimuli group is selected. One or more scan chains that are not in the stimuli group and are needed for observing the large number of faults are assigned to a compacting group. The number of scan chains either in the compacting group or in both of the compacting group and the stimuli group may be limited to a predetermined number.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: April 7, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
  • Methods and system for analysis and management of parametric yield
    Patent number: 8997028
    Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: March 31, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
  • Test data volume reduction based on test cube properties
    Patent number: 8996941
    Abstract: Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 31, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Janusz Rajski
  • Cell-aware fault model generation for delay faults
    Patent number: 8990760
    Abstract: Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: March 24, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Friedrich Hapke, Wilfried Redemund, Juergen Schloeffel, Andreas Glowatz