Patents Assigned to Mentor Graphics
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Patent number: 9372946Abstract: Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated.Type: GrantFiled: August 22, 2013Date of Patent: June 21, 2016Assignee: Mentor Graphics CorporationInventor: Stephen Kenneth Sunter
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Publication number: 20160161551Abstract: The disclosed technology relates to analyzing an electronic board having a plurality of FPGAs that are interconnected and programmed to implement a logic design. One example method comprises: setting up a graph representing the board; determining, for each FPGA, by means of an FPGA-specific static temporal analysis tool, the time for travelling over each path portion that passes through said FPGA, each travel time corresponding to the sum of the times for carrying out the logical operations applied to the signal in the FPGA; determining the inter-FPGA time for travelling over each inter-FPGA portion represented by a link in the graph; and determining the time for travelling over each path of the board by summing the intra-FPGA travel times and the inter-FPGA travel times associated with each link of the graph.Type: ApplicationFiled: July 8, 2014Publication date: June 9, 2016Applicant: Mentor Graphics CorporationInventors: Matthieu Tuna, Zied Marrakchi, Christophe Alexandre
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Patent number: 9361422Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.Type: GrantFiled: October 21, 2013Date of Patent: June 7, 2016Assignee: Mentor Graphics CorporationInventors: James Word, Nicolas B. Cobb, Patrick J. LaCour
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Patent number: 9361424Abstract: A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.Type: GrantFiled: August 4, 2014Date of Patent: June 7, 2016Assignee: Mentor Graphics CorporationInventor: Juan Andres Torres Robles
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Patent number: 9355201Abstract: The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.Type: GrantFiled: August 19, 2013Date of Patent: May 31, 2016Assignee: Mentor Graphics CorporationInventor: Yuri Granik
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Patent number: 9347993Abstract: Aspects of the invention relate to test generation techniques for test-per-clock. Test cubes may be generated by adding constraints to a conventional automatic test pattern generator. During a test cube merging process, a first test cube is merged with one or more test cubes that are compatible with the first test cube to generate a second test cube. The second test cube is shifted by one bit along a direction of scan chain shifting to generate a third test cube. The third test cube is then merged with one or more test cubes in the test cubes that are compatible with the third test cube to generate a fourth test cube. The shifting and merging operations may be repeated for a predetermined number of times.Type: GrantFiled: June 17, 2013Date of Patent: May 24, 2016Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
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Publication number: 20160136899Abstract: Methods and apparatus are disclosed for symbolic methods using algebraic geometry (e.g., based on a Gröbner basis of tangent space polynomials of parametric curves). For example, the design, optimization and verification of silicon photonic wave guides using parametric polynomials and/or Gröbner basis functions can be used to perform envelope generation, rectification, manufacturability checking, singularity detection, reticle and etch processing model generation, tapering loss minimization, and bend loss minimization. In one example, a method of analyzing a layout to be manufactured using a photolithographic process includes producing an envelope of a curve representing a layout object based at least in part on a Gröbner basis and performing one or more analysis operations for the envelope to perform verification and manufacturability checks.Type: ApplicationFiled: January 20, 2016Publication date: May 19, 2016Applicant: Mentor Graphics CorporationInventor: Sandeep Koranne
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Patent number: 9335377Abstract: Aspects of the invention relate to a test-per-clock scheme based on dynamically-partitioned reconfigurable scan chains. Every clock cycle, scan chains configured by a control signal to operate in a shifting-launching mode shift in test stimuli one bit and immediately applies the newly formed test pattern to the circuit-under-test; and scan chains configured by the control signal to operate in a capturing-compacting-shifting mode shift out one bit of previously compacted test response data while compacting remaining bits of the previously compacted test response data with a currently-captured test response to form currently compacted test response data. A large number of scan chains may be configured by the control signal to work in a mission mode. After a predetermined number of clock cycles, a different control signal may be applied to reconfigure and partition the scan chains for applying different test stimuli.Type: GrantFiled: June 17, 2013Date of Patent: May 10, 2016Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski
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Patent number: 9335376Abstract: The disclosed ring-oscillator-based test architecture comprises a plurality of boundary scan cells coupled to a plurality of interconnects and control circuitry. Each of the plurality of boundary scan cells can be configured to operate as, based on control signals, a conventional boundary scan cell or any bit of an asynchronous counter. The control signals are supplied by the control circuitry.Type: GrantFiled: February 18, 2014Date of Patent: May 10, 2016Assignee: Mentor Graphics CorporationInventors: Wu-Tung Cheng, Ruifeng Guo, Yu Huang, Liyang Lai, Jing Ye, Yu Hu
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Patent number: 9336107Abstract: Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.Type: GrantFiled: November 19, 2012Date of Patent: May 10, 2016Assignee: Mentor Graphics CorporationInventors: Huaxing Tang, Yu Huang, Wu-Tung Cheng, Robert Brady Benware, Xiaoxin Fan
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Patent number: 9335374Abstract: Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.Type: GrantFiled: December 2, 2014Date of Patent: May 10, 2016Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Mark A. Kassab, Janusz Rajski
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Patent number: 9330228Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern is constructed based on seeding positions for a via-type feature group. The initial seeding positions are derived from targeted locations of via-type features in the via-type feature group. A potential energy function is then determined for the guiding pattern. Based on the potential energy function, simulated locations of the via-type features are computed. The seeding positions are compared with the targeted locations and may be adjusted based on differences between the simulated locations and the targeted locations. The above operations may be repeated until one of one or more termination conditions are met.Type: GrantFiled: April 22, 2015Date of Patent: May 3, 2016Assignee: Mentor Graphics CorporationInventors: Juan Andres Torres Robles, Joydeep Mitra, Yuansheng Ma, Krasnova Polina Andreevna, Yuri Granik
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Patent number: 9330226Abstract: Aspects of the disclosed techniques relate to techniques for modeling substrate noise coupling. Electrical impedance between two contacts in the presence of one or more other contacts is modeled based on a horizontal impedance model and an L-shaped impedance model. The one or more other contacts may be clustered together in four regions first and then are represented by the horizontal impedance model and/or the L-shaped impedance model. The electrical impedance is inserted into netlist for circuit simulation.Type: GrantFiled: October 7, 2014Date of Patent: May 3, 2016Assignee: Mentor Graphics CorporationInventors: Mohamed Saleh Abouelyazid Saleh, Alaa El-Deen Barakat Ahmed El-Rouby
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Patent number: 9323632Abstract: A method and system is disclosed for monitoring and viewing physical parameters while the emulator is emulating a design. Additionally, the parameters are in real time or substantially real time, such as after a periodic update. In one embodiment, a monitoring portion of the emulator periodically monitors the emulator boards and power supplies for physical information. The physical information is communicated to a workstation for communication to a user. For example, the workstation can display the physical information in a graphical user interface (GUI) that shows which boards are plugged in the system and which slots are empty. In yet another aspect, the user can select a particular board in the system and view communication information, such as data errors, status, link errors, global errors, etc.Type: GrantFiled: May 10, 2012Date of Patent: April 26, 2016Assignee: Mentor Graphics CorporationInventors: Eric Durand, Christophe Joubert, Christian Niquet, Virginie Voirin
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Patent number: 9323873Abstract: A method for simulating behavior of first and second interrelated components within a system. The method comprises modelling behavior of said first and second components using first and second functional specifications; simulating behavior of said first and second components in predetermined circumstances by instantiating at least one first entity within a hierarchy of interrelated entities; and instantiating at least one further entity in response to the or each instantiated first entity. The or each further entity is selected by a simulation system on the basis of its hierarchical relationship with the at least one first entity.Type: GrantFiled: December 19, 2011Date of Patent: April 26, 2016Assignee: Mentor Graphics CorporationInventors: Steven Hodgson, Jason Sotiris Polychronopoulos, Christopher Jones, Zakwan Shaar, Muhammed Mutaher Kamal Hashmi, Len Theobald, Wilfred Barry Hughes
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Patent number: 9323161Abstract: A system and method for optimizing an illumination source to print a desired pattern of features dividing a light source into pixels and determining an optimum intensity for each pixel such that when the pixels are simultaneously illuminated, the error in a printed pattern of features is minimized. In one embodiment, a method includes selecting a pattern of layout features by determining one or more periodic patterns of features that occurs in the layout database, defining a mathematical relationship between pixel intensities produced by a diffractive optical element and the selected pattern of features, where the mathematical relationship includes a heavier weighting for the periodic patterns of features, and assigning pixel intensities for the diffractive optical element using the mathematical relationship, where the pixel intensities are calculated to print the periodic features with greater image fidelity in proportion to the heavier weighting.Type: GrantFiled: October 26, 2009Date of Patent: April 26, 2016Assignee: Mentor Graphics CorporationInventor: Yuri Granik
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Patent number: 9310831Abstract: A method for building a clock tree for an integrated circuit design. The clock tree has a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design to distribute the clock signal to the sink pins, which are clustered into one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters.Type: GrantFiled: October 14, 2011Date of Patent: April 12, 2016Assignee: Mentor Graphics CorporationInventors: Sivaprakasam Sunder, Kirk Schollman
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Patent number: 9305126Abstract: Aspects of the invention relate to techniques for using retiming to reduce circuit switching activity. Switching activity values at output ports of circuit elements of a circuit design are first computed based on switching activity values at input ports of the circuit elements and scaling factors associated with the circuit elements. Based on the switching activity values at the output ports of the circuit elements, one or more regions of the circuit design for retiming are identified. Retiming location information is then determined for the one or more regions. Finally, the identified one or more regions are then retimed to reduce switching activity based on the retiming location information.Type: GrantFiled: March 21, 2014Date of Patent: April 5, 2016Assignee: Mentor Graphics CorporationInventors: Charles W. Selvidge, Sanjay Gupta, Praveen Shukla, Saurabh Gupta, Jeffrey Evans
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Patent number: 9304881Abstract: Hardware emulation produces relevant and irrelevant trace data. Verification of a design under test requires knowledge of the relevant trace data. Data lines are provided to capture trace data from the hardware emulator's logic elements during emulation. The data lines connect the outputs of these logic elements to the inputs of a configurable interconnect circuit. The configurable interconnect circuit is capable of being programmed to select from a plurality of these inputs to connect a number of the data lines to a scan chain or trace data storage circuit. The configurable interconnect circuit can then selectively connect those data lines carrying relevant trace data to a trace data processing circuit. The trace data processing circuit may be a scan chain, analysis device or storage device or other suitable trace data processing device.Type: GrantFiled: October 16, 2013Date of Patent: April 5, 2016Assignee: Mentor Graphics CorporationInventors: Cyril Quennesson, Pamphile Koumou
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Patent number: 9292643Abstract: A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to include only those designated cover cells. Non-designated cover cells and other geometric data are flattened into the designated cover cells. The hierarchy of the modified file is then redefined to be less than or equal to the hierarchy limit of the mask writing tool.Type: GrantFiled: May 10, 2010Date of Patent: March 22, 2016Assignee: Mentor Graphics CorporationInventors: Emile Y. Sahouria, Weidong Zhang