Abstract: This application discloses a computing system implementing a schematic capture tool to utilize physical test capabilities of a manufacturer of a printed circuit board assembly during generation of a logical design for the printed circuit board assembly. The schematic capture tool can utilize the physical test capabilities of the manufacturer to trim a list of parts representing electronic components available for use in the printed circuit board assembly, and generate the logical design for the printed circuit board assembly utilized the trimmed list of parts. The schematic capture tool can utilize the physical test capabilities of the manufacturer to determine which nets in the logical design to assign test points. The schematic capture tool can provide an indication of the assigned test points to a layout tool, which can include the test points in a layout design for the printed circuit board assembly based on the assignment.

Abstract: A method for simulating behavior of first and second interrelated components within a system. The method comprises modelling behavior of said first and second components using first and second functional specifications; simulating behavior of said first and second components in predetermined circumstances by instantiating at least one first entity within a hierarchy of interrelated entities; and instantiating at least one further entity in response to the or each instantiated first entity. The or each further entity is selected by a simulation system on the basis of its hierarchical relationship with the at least one first entity.

Abstract: Aspects of the disclosed technology relate to techniques for modeling content-addressable memory in emulation and prototyping. A model for content-addressable memory comprises memory circuitry configured to store match results for various search keys. The match results are stored in the second memory circuitry during write operations. The model for content-addressable memory may further comprise additional memory circuitry configured to operate as a standard computer memory, performing read operations alone and write operations along with the memory circuitry.

Abstract: A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second simulation model without simulating the transfer through the simulated circuit design.

Abstract: This application discloses a computing system configured to divide bins into primary bins and secondary bins based, at least in part, on a configuration of a circuit design describing an electronic device. The computing system can utilize the primary bins to record coverage events performed by the electronic device when modeled in a verification environment by the computing system, and infer coverage event records for the secondary bins based, at least in part, on the coverage event records for the primary bins.

Abstract: This application discloses a supply chain security technique that enrolls an integrated circuit with a security server and subsequently utilizes the enrollment to authenticate the integrated circuit. The integrated circuit can include security circuitry to enroll the integrated circuit with the security server by generating an enrollment message—including a fingerprint code having an encoded version of a private value generated by the security circuitry—for transmission to the security server. The security circuitry can authenticate the integrated circuit by replying to a request to verify authentication of the integrated circuit from the security server. The response can confirm to the security server that the integrated circuit includes the private value, which can authenticate the integrated circuit.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems for performing power analysis during the design and verification of a circuit. Certain exemplary embodiments include user interfaces and software infrastructures that provide a flexible and powerful environment for performing power analysis. For example, embodiments of the disclosed technology can be used to construct complex and targeted power queries that quickly provide a designer with power information during a circuit design process. The disclosed methods can be implemented by a software tool (e.g., a power analysis tool or other EDA tool) that computes and reports power characteristics in a circuit design (e.g., a system-on-a-chip design or other integrated design).

Abstract: Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.

Abstract: Systems and methods for validating a circuit design are described. The circuit validation includes determining a subset of checks to apply to a portion of the overall circuit based on the pin type composition of the circuit portion.

Abstract: This application discloses an device disposed on a substrate, and a heat sink disposed on the substrate over the device. The heat sink disposed on the substrate forms a cavity to hold a fluid between the heat sink and the device. The fluid can absorb heat emitted by the device and transfer at least a portion of the absorbed heat to the heat sink. A gasket can be disposed between and in contact with the substrate and the heat sink. The gasket can prevent the fluid from exiting the cavity formed by the heat sink disposed on the substrate. The heat sink can have an opening to the cavity, which can be detachably sealed by a plug. The plug can reduce a pressure within the cavity or allow removal of gas bubbles in the fluid held in the cavity.

Abstract: This application discloses a design verification tool to generate an interconnect between portions of a circuit design in a mixed language environment. The design verification tool can select an interconnect generation technique based on characteristics for the portions of the circuit design and, during elaboration of the circuit design, utilize the selected interconnect generation technique to generate the interconnect. The design verification tool can generate the interconnect without the circuit design including code to identify the selected interconnect generation technique to the design verification tool. The design verification tool can perform functional verification operations on the elaborated circuit design, and modify results of the functional verification operations to remove an intermediate hierarchy utilized to generate the interconnect during elaboration. The modified results can show the portions of the circuit design being directly connected by the interconnect.

Abstract: In one embodiment, a method for performing an analysis of a synthesized clock tree can include: displaying a plurality of variation parameters and one or more analysis values on a display screen; accepting a first signal from a user input device to select one of the variation parameters; accepting a second signal from a user input device to select one or more of the analysis values; and displaying a plurality of pins from the synthesized clock tree with the selected variation parameter and the selected one or more analysis values on the display screen.

Abstract: This application discloses a computing system to select a design block in a circuit design of an electronic device for functional verification result reuse based on isolating operational characteristics of the design block. The computing system can determine whether the selected design block was previously simulated with input stimulus. When the selected design block was previously simulated with the input stimulus, the computing system can bypass the simulation of the design block and utilize an output generated in the previous simulation of the selected design block in response to the input stimulus as a result for the simulation of the design block. When the selected design block was not previously simulated with the input stimulus, the computing system can simulate the selected design block with the input stimulus, and storing an output generated in the simulation of the selected design block for functional verification result reuse.

Abstract: Aspects of the disclosed technology relate to techniques of parasitic extraction. A signature for a set of geometric elements of a layout design is computed based on contour-related information. The set of geometric elements corresponds to a net of connected equipotential interconnects of a circuit design. Based on comparing the signature with signatures for sets of geometric elements that have computed parasitic element values, parasitic element values for the set of geometric elements are determined.

Abstract: Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.

Abstract: Aspects of the disclosed technology relate to techniques of scoped simulation-based ESD verification. ESD (electrostatic discharge) protection devices and I/O (input/output) circuitry are identified in a circuit design. Static simulation is performed on the I/O circuitry to determine voltage and current information for devices on current paths in the I/O circuitry based on point-to-point resistance values. Transient simulation is then performed on one or more of the ESD protection devices in the devices based on the voltage and current information and detailed parasitic information. The point-to-point resistance values and the detailed parasitic information are extracted based on a layout design for the circuit design and cross-reference information between circuit component identifiers and layout features. Results of the transient simulation are analyzed to identify ESD protection problems.

Abstract: This application discloses a computing system configured to determine that a first bind command is configured to prompt instantiation of an assertion module in a target module of a circuit design, which creates a mixed-language environment for the circuit design. The computing system, in response to the determination that the first bind command is configured to create the mixed-language environment for the circuit design, configured to generate a wrapper module configured to prompt instantiation of the assertion module in the wrapper module. The computing system configured to generate a second bind command configured to prompt instantiation of the wrapper module in the target module.

Abstract: Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.

Abstract: This application discloses a computing system to parse a product model definition that includes a layout design of a printed circuit board assembly, which identifies physical design characteristics of the layout design of the printed circuit board assembly. The computing system can identify one or more manufacturing processes capable of manufacturing at least a portion of the printed circuit board assembly having the identified physical design characteristics. The computing system can include a map or correlation between the manufacturing processes and manufacturing-related design constraints. The computing system can select one or more manufacturing checks that define manufacturing-related design constraints correlated to the identified manufacturing processes.

Abstract: This application discloses a computing system to identify multiple views of cells in a circuit design for selective utilization during analog fault simulation of the circuit design. The views of the cells can include two or more of macromodel design views, schematic design views, or extracted design views that includes parasitic elements extracted from a physical layout of the circuit design. The computing system can prompt generation of multiple netlists, each netlist generated based on a different combination of the identified views of the cells in the circuit design, or a list of macromodels with pin accurate subcircuit wrappers, parse and organize the cells in each netlist or the list of macromodels, identify one of the cells to inject with a defect, and selectively simulate portions from a plurality of the netlists based, at least in part, on the identified one of the cells to inject with the defect.