Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.

Abstract: This application discloses a physical unclonable function device including physical unclonable function units, each capable of generating an output. The physical unclonable function device can utilize transforms to derive bits from the outputs and utilize the derived bits to generate an identifier for the physical unclonable function device. An inspection configuration tool can sample multiple outputs from each of the physical unclonable function units, identify a transforms to perform on a future output for each of the physical unclonable function units based on a distribution of values corresponding to the sampled outputs. The inspection configuration tool can configure the physical unclonable function device to perform the transforms on the future outputs of the physical unclonable function units. Embodiments will be described below in greater detail.

Abstract: A computer-implemented method for quickly analyzing the effect of process, voltage, temperature, and other variations when the variation analysis or circuit structure can be hierarchically composed into nested loops. The method has two main steps: first, it hierarchically generates a set of points and inserts them into a flat list of tuples, where each tuple contains a point from each level in the looping hierarchy. Second, it efficiently identifies and simulates failing tuples with the assistance of modeling to order the tuples to simulate. By using the present method, a designer does not have to simulate the full ECD at each and every statistical process point or PVT corner, which can same considerable time or compute effort.

Abstract: This application discloses a computing system configured to determine a timing window for reception of a signal propagated through a victim channel in a circuit design, generate an aggressor window bump for each noise bump capable of being induced on the victim channel by one or more aggressor channels, determine a delta delay corresponding to the timing window for the signal propagated through the victim channel based, at least in part, on one or more of the aggressor window bump, and utilize the delta delay corresponding to the timing window for the signal to determine whether the victim channel operates within a timing constraint associated with the circuit design.

Abstract: A control server facilitates communication between a tool server hosting an instance of a software tool and a client device employed by a user of the software tool. The client device initially contacts the control server to request the use of the software tool. The control server then arranges for a separate computer to be configured as a tool server that can provide remote access to an instance of the software tool. The control server may provide usage information to the tool server that will control how the software tool may be used. The control server may also provide connection information to the client device, which the client device then can use to establish a connection with the tool server. Using the connection information, the client device then establishes a remote connection with the tool server, allowing the user of the client device to use the software tool hosted on the tool server through the remote connection.

Abstract: Various aspects of the disclosed technology relate to axial thrust analysis of turbomachinery designs. A cavity of a turbomachinery design is divided into sub-cavities. Magnitudes of horizontal components of forces exerted on rotational faces in each of the sub-cavities are computed based on computational fluid dynamics, areas of the rotational faces and angles of the rotational faces. The horizontal components are components along a rotational axis of the turbomachinery design. Directions of the horizontal components of the forces are determined based on how many faces a line parallel to the rotational axis intersects between a rotational face of interest and a side of the cavity. A thrust force on a turbine of the turbomachinery design attributed to secondary fluid systems is computed using the magnitudes and the directions of the horizontal components of the forces.

Abstract: This application discloses tools and mechanisms to convert a program from a sequentially-executable format into a parallel-executable format, and then modify the program in the parallel-executable format to either allow compilation for parallel execution or to speed-up the parallel execution by an accelerated processing unit. The tools and mechanisms can identify various features of the program, such as recursive calls, search loops, inline function calls, uncompressed data structures, memory utilization, and inter-dependent kernel instances. The tools and mechanisms can modify the program to replace or otherwise augment the identified features, which can allow the modified program to be compiled for parallel execution, or speed-up the parallel execution by an accelerated processing unit.

Abstract: An integrated circuit for on-chip speed grading comprises test circuitry comprising scan chains and a test controller; and wide-range clock signal generation circuitry comprising phase-locked loop circuitry and frequency divider circuitry. The wide-range clock signal generation circuitry is configured to generate a wide-range test clock signal for the test circuitry to conduct a structural delay test for on-chip speed grading. The wide-range test clock signal is generated based on a test clock signal associated with the test circuitry, a frequency range selection signal and a frequency setting signal.

Abstract: This application discloses a computing system to implement low-level sensor fusion in an assisted or automated driving system of a vehicle. The low-level sensor fusion can include receiving raw measurement data from sensors in the vehicle and temporally aligning the raw measurement data based on a time of capture. The low-level sensor fusion can include spatially aligning measurement coordinate fields of the sensors into an environmental coordinate field based, at least in part, on where the sensors are mounted in the vehicle, and then populating the environmental coordinate field with raw measurement data captured by the sensors based on the spatial alignment of the measurement coordinate fields to the environmental coordinate field. The low-level sensor fusion can detect at least one detection event or object based, at least in part, on the raw measurement data from multiple sensors as populated in the environmental coordinate field.

Abstract: Aspects of the disclosed technology relate to techniques of pattern matching. Matching rectangles in a layout design that match rectangle members of a search pattern are identified based on edge operations. The rectangle members comprise an origin rectangle member and one or more reference rectangle members. Grid element identification values are attached to the matching rectangles. The matching rectangles that match the one or more reference rectangle members in neighborhoods of the matching rectangles that match the origin rectangle member are then analyzed. The neighborhoods are determined based on the grid element identification values. Based on the analysis, matching patterns in the layout design that match the search pattern are determined.

Abstract: Aspects of the disclosed technology relate to techniques of generating guiding patterns for via-type features. An initial guiding pattern characterized by a plurality of guiding pattern parameters is constructed for two or more via-type features in a layout design based on target values of location and size parameters for the two or more via-type features. Predicted values of the location and size parameters are then extracted from the initial guiding pattern based on simulations or correlation information between the plurality of guiding pattern parameters and the location and size parameters. Based on the predicted values of the location and size parameters, the target values of location and size parameters and the correlation information, a modified guiding pattern is determined by adjusting one or more parameters of the plurality of guiding pattern parameters. The extraction and determination operations may be iterated.

Abstract: Layout design data is seeded with sampling markers. The sampling markers are used to determine patterning scores for patterning clusters in the layout design data, such that a patterning score corresponds to a particular coloring arrangement, and the value of a patterning score corresponds to how many of the sampling markers have a given color. Coloring arrangements are then applied to the patterning clusters based upon the patterning scores.

Abstract: This application discloses a computing system implementing tools and mechanisms to generate a composite solid model for a set of parts and utilize the composite solid model during the layout process. The tools and mechanisms can identify multiple parts available for inclusion in a circuit design, combine component models corresponding to the multiple parts into a composite solid model, and place the composite solid model in the layout representation of the circuit design. The composite solid model can have physical dimensions that overlap with physical dimensions of the component models corresponding to the multiple parts.

Abstract: Methods and apparatus for dynamic distributed resource management as can be used in large-scale electronic design automation processes, are disclosed. In some examples of the disclosed technology, a method for dynamic remote resource allocation includes receiving a request for one or more remote resources, identifying one or more resources available to satisfy the request, initiating one or more separate processes for the respective available resources, preparing the respective resources for use as remote resources, by the one or more separate processes running in parallel, and as a given resource of the one or more available resources completes the preparation, allocating the given resource as a remote resource. In some examples, allocated resources are dynamically integrated into the processing of the job. In some examples, as a given resource of the one or more available resources is allocated, tasking the given resource with a portion of the job.

Abstract: This application discloses an electronic system including active circuitry configured to be selectively enabled for authorized number of times. The electronic system also includes security circuitry to detect an enablement event associated with the electronic system. The enablement event can correspond to reception of a reset signal associated with the electronic system, a lapse of a predetermined time period, or the like. In response to the detection of the enablement event, the security circuitry can determine a number of times the security circuitry has previously enabled the active circuitry. The security circuitry can generate the enablement signals capable of enabling the active circuitry when the determined number of times the security circuitry has previously enabled the active circuitry is fewer than the authorized number of times.

Abstract: This application discloses a computing system to implement a place and route tool to synthesize a clock tree in a layout design of an integrated circuit based on timing constraints for the integrated circuit. The computing system can select a portion of the clock tree to present in a schematic connectivity presentation based on a conformance of the portion of the clock tree to timing constraints for the clock tree. The computing system can compress the other portions of the clock tree into the compacted representation based on the selection of the portion of the clock tree. The compacted representation can retain a hierarchical connectivity of the other portions of the clock tree. The computing system can generate the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree coupled to at least one compacted representation of other portions of the clock tree.

Abstract: A system and method for optimizing an illumination source to print a desired pattern of features dividing a light source into pixels and determining an optimum intensity for each pixel such that when the pixels are simultaneously illuminated, the error in a printed pattern of features is minimized. In one embodiment, pixel solutions are constrained from solutions that are bright, continuous, and smooth. In another embodiment, the light source optimization and resolution enhancement technique(s) are iteratively performed to minimize errors in a printed pattern of features.

Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Abstract: Various aspects of the disclosed technology relate to circuit defect diagnosis based on sink cell fault models. Defect candidates are determined based on path-tracing from failing bits into the circuit design. Based on the defect candidates and one or more conventional fault models, failing test pattern simulations are performed to determine initial defect suspects. Initial defective sink cell suspects are then determined by comparing driving strengths for fan-out cells of the initial defect suspects with driving strengths for corresponding driver cells. Defective sink cell suspects may be identified in the initial defective sink cell suspects based on fault effect propagations and passing test pattern simulations.

Abstract: This application discloses a computing system to perform a fast evaluation of a worst case eye diagram for a channel capable of communicating signals encoding data in more than two value levels. The computing system can identify multiple step responses of the channel, each corresponding to a transition between a plurality of the value levels. The computing system can determine distribution boundaries of the signals at each of the value levels based, at least in part, on the step responses of the channel. The computing system can utilize the distribution boundaries at the value levels to determine boundaries of eye openings between adjacent value levels or to build worst case input patterns used to generate the worst case eye diagram for the channel. The computing system can predict a signal integrity of the channel based on the distribution boundaries at each of the value levels.