Abstract: A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when an interpolator rollover event of a phase integer portion of a phase interpolator has occurred, and a correction circuit that adds a signed predistortion correction to the VCO clock cycle fraction value of the phase interpolator when the rollover detector circuit has detected the interpolator rollover event.

Abstract: A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.

Abstract: A method for operating a storage controller to write to a group of multi-actuator disk drives includes receiving a data stream, performing RAID mapping to a preselected RAID level, organizing the data stream into at least one data stream, creating at least one parity data stream, organizing each data stream and parity data stream into blocks of data, dividing each data stream and each parity data stream into groups of blocks of data assigned to a logical unit representing a drive and an actuator, blocks of data from a data stream and parity stream assigned to a different drive, sequential groups of blocks of data assigned substantially equally to logical units representing actuators in each drive, providing each group of blocks of data to a target port associated with the drive to which it has been assigned, and sending each group of blocks of data from the target port.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A packaged electronic die having a micro-cavity and a method for forming a packaged electronic die. The packaged electronic die includes a photoresist frame secured to the electronic die and extending completely around the device. The photoresist frame is further secured to a first major surface of a substrate so as to form an enclosure around the device. Encapsulant material extends over the electronic die and around the sides of the electronic die. The encapsulant material is in contact with the first major surface of the substrate around the entire periphery of the electronic die so as to form a seal around the electronic die.

Abstract: A system and method for data sampler drift compensation in a SerDes receiver. Off-data values are received at a drift compensation engine from a plurality of data value selectors coupled to one of a plurality of data sampler pairs of a speculative Decision Feedback Equalizer (DFE) of a SerDes receiver. A drift compensation value for each of the data samplers is generated by the drift compensation engine based upon the off-data values received from each of the plurality of data value selectors and, a sampling level of each of the data samplers of the plurality of data sampler pairs of the DFE is adjusted based upon the drift compensation value from the drift compensation engine.

Abstract: A circuit for transferring a n-bit phase value between circuits includes a system clock input, a n-bit phase value generator coupled to the system clock input generating a phase value output, and an edge output indicating the phase output value is valid, a latching clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to the control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to the output of the variable phase delay circuit, a clock input coupled to a latching clock output of the variable output clock delay circuit and a Phase Out output.

Abstract: A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.

Abstract: A method for writing data to a dual-actuator disk drive includes providing a multi-actuator disk drive having a first actuator communicating with first disk platters and a second actuator communicating with second disk platters, receiving in a storage controller coupled to the disk drive a data stream including groups of blocks of data to be written to the multi-actuator disk drive, alternately distributing from a disk controller in the disk drive sequential ones of the groups of blocks of data from the data stream to the first actuator and the second actuator as defined by commands from the storage controller, and simultaneously writing from the first actuator to the at least one first disk platter ones of the groups of blocks of data routed to the first actuator and writing from the second actuator to the at least one second disk platter ones of the groups of blocks of data routed to the second actuator.

Abstract: A method for extracting path overhead (POH) data blocks from a data stream in a 64B/66B-block communication link, the method includes receiving at a sink node a data stream in a 64B/66B-block communication link, detecting within the data stream at a PCS sublayer a micro-packet starting with an /S/ control block, including K POH data blocks, and ending with a /T/ control block, extracting the micro-packet from the data stream, and extracting the POH data blocks from the micro-packet.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A method and apparatus for decoding are disclosed. The method includes receiving a first Forward Error Correction (FEC) block of read values, starting a hard-decode process in which a number of check node failures is identified and, during the hard-decode process comparing the identified number of check node failures to a decode threshold. When the identified number of check node failures is not greater than the decode threshold the hard-decode process is continued. When the identified number of check node failures is greater than the decode threshold, the method includes: stopping the hard-decode process prior to completion of the hard-decode process; generating output indicating that additional reads are required; receiving one or more additional FEC blocks of read values, mapping the first FEC block of read values and the additional FEC blocks of read values into soft-input values; and performing a soft-decode process on the soft-input values.

Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.

Abstract: A ReRAM memory cell includes a ReRAM element, a programming circuit coupled to the ReRAM element and defining a programming circuit path in the ReRAM memory cell, and an erase circuit coupled to the ReRAM element and defining an erase circuit path in the ReRAM memory cell. The programming circuit path is separate from the erase circuit path.

Abstract: A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

Abstract: A high-voltage termination for a semiconductor device includes a substrate of a first conductivity type, an implanted device region of a second conductivity type of the semiconductor device, a shallow trench disposed in the substrate adjacent to the implanted device region, a doped extension region of the second conductivity type extending between the implanted device region and a first edge of the shallow trench adjacent to the implanted device region, a junction termination extension region of the second conductivity type formed in the shallow trench contacting the extension region and extending past a second edge of the shallow trench opposite the implanted device region, an insulating layer formed over at least a portion of the extension region and over the junction termination extension region, and a metal layer formed over the insulating layer extending into at least a portion of the shallow trench and electrically connected to the extension region.

Abstract: A reverse power feeding (RPF) power supply unit (PSU) for remote network distribution point unit (DPU) that is reverse powered from multiple customer premise equipments (CPEs). A plurality of power converters, each having a different primary winding and sharing a common secondary winding of a transformer at the PSU, wherein only one of the power converters is operated at a time to provide a desired output voltage.

Abstract: An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.

Abstract: A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

Abstract: A phase predictor to accurately detect and predict the phase relationship between two clocks running at different frequencies. The phase relationship can be used to record the transmission and reception times of Ethernet frames transmitted over a transmission medium with very high accuracy.