Abstract: A device is disclosed. In one or more examples, the device may include an antenna to receive a signal encoding timing information for one or more of positioning, navigation, and timing. The signal may include a pulse group comprising a number of ranging pulses and a number of data pulses subsequent to the number of ranging pulses. Respective ones of the number of data pulses may have a phase of either a positive-going phase or a negative-going phase. Data may be encoded using the either positive-going phases or negative-going phases of the data pulses. The device may include a processor to decode the data at least partially responsive to the phases of the respective ones of the number of data pulses.

Abstract: Object detection for wireless power transmitters and related systems, methods, and devices are disclosed. A controller for a wireless power transmitter is configured to receive a measurement voltage potential responsive to a tank circuit signal at a tank circuit, provide an alternating current (AC) signal to each of the plurality of transmit coils one at a time, and determine at least one of a resonant frequency and a quality factor (Q-factor) of the tank circuit responsive to each selected transmit coil of the plurality of transmit coils. The controller is also configured to select a transmit coil to use to transmit wireless power to a receive coil of a wireless power receiver responsive to the determined at least one of the resonant frequency and the Q-factor for each transmit coil of the plurality of transmit coils.

Abstract: One or more examples relate to a detector. A signal that the detector is configured to sense is a differential value. Such a differential value may be indicative of a difference in self-capacitance indications that are exhibited at first and second internal capacitors. Such a differential value may be proportional to a relationship between a first material and a second material present at a device-under-test coupled to electrodes of the detector. Such a differential value may be proportional to a vertical elevation of a surface of a material present at a device-under-test coupled to electrodes of the detector. A difference in coupling capacitances may be obtained by performing complimentary acquisition processes utilizing symmetric capacitive sensors. When the acquisition processes are performed substantially simultaneously, coupling error indications that may be present in the self-capacitance indications are not present in the differential value.

Abstract: Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.

Abstract: A redundant angular position sensor comprising a first angular position sensor including a first excitation coil, a first sensing coil and a second sensing coil and a second angular position sensor. The second angular position sensor including a second excitation coil, a third sensing coil and a fourth sensing coil. Each of the first, second, third and fourth sensing coils comprising a respective clockwise winding portion and a respective counter-clockwise winding portion. The redundant angular position sensor further comprises a rotatable inductive coupling element positioned in overlying relation to the sensing coils and separated from the sensing coils by a gap, wherein the rotatable inductive coupling element comprises four, substantially evenly radially spaced, sector apertures.

Abstract: A system and method transmit a data stream from a source to a destination over a communication channel. A transmitter includes devices for processing inputs to assemble data packets for the data stream, and a multiplexer for assembling a data frame to be transmitted over the communication channel, in which each data frame has at least one fixed slot. The multiplexer sets at least one freely allocatable time slot in each data frame. Retransmission control devices connected to the multiplexer retransmit a specific data packet which is not properly received by the destination, using one of the freely allocatable slots.

Abstract: Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system.

Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

Abstract: A remote control system for opening and closing a barrier, such as a garage door, includes an RF receiver and a plurality of RF transmitters. The transmitters and receiver include circuitry programmed to provide transmission of encrypted code signals each time the transmitters are used and employing a code hopping method which prevents unauthorized signal interception or code “grabbing”. The system is operated in a code learning mode for the receiver by momentarily actuating a receiver learn mode button for receiving each transmitter identification code and a secret decryption key for that transmitter with the system automatically returning to the operate mode. Each transmitter identification and secret key code signal is automatically and randomly stored in an available and unused memory in the receiver circuitry.

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Abstract: A method and system for the remote control of devices having a secure self learn capability. The system includes an encoder and a decoder, the encoder encoding variable information including a user key using a non-linear algorithm to produce an encoded value transmitted to the decoder, the decoder decoding the value using the same algorithm. In a learning mode a new encoder is to be added to the system. The new encoder produces an encoded value using a key generation seed. The decoder, upon receiving the encoded key generation seed, produces a decoding key based upon the decoded key generation seed. The decoding key is stored in the decoder memory allowing valid recognition of the new encoder in a secure manner.

Abstract: A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter for monitoring a number of specified events. A data storage device is coupled to the counter for loading the counter with counter values for each of the contiguous counts. A control logic circuit is coupled to the counter and to the data storage circuit for loading the counter and the data storage device with the counter values.

Abstract: An integrated circuit having a microcontroller, mask programmed read only memory, functions such as clock oscillator, analog-to-digital converter, timers, etc., where each may be adjusted with a digital input to a desired calibration value. The digital input resulting in the desired calibration value being stored in a programmable fuse array.

Abstract: A remote control system for opening and closing a barrier, such as a garage door, includes an RF receiver and a plurality of RF transmitters. The transmitters and receiver include circuitry programmed to provide transmission of encrypted code signals each time the transmitters are used and employing a code hopping method which prevents unauthorized signal interception or code "grabbing". The system is operated in a code learning mode for the receiver by momentarily actuating a receiver learn mode button for receiving each transmitter identification code and a secret decryption key for that transmitter with the system automatically returning to the operate mode. Each transmitter identification and secret key code signal is automatically and randomly stored in an available and unused memory in the receiver circuitry.

Abstract: According to the present invention, there is provided an integrated circuit useful in an electronic encoding device having a voltage source, a user interface and a transmitter. In one embodiment the integrated circuit includes a wake-up circuit which generates a signal responsive to an input received from the user interface; power switching logic which provides power from the voltage source to a non-regulated power bus and a voltage regulating circuit, the power switching logic being responsive to the signal from the wake-up circuit; a regulated power bus in communication with the voltage regulating circuit; non-volatile memory in communication with the regulated power bus; encoder logic in communication with the regulated power bus, the encoder logic having output logic which provides a signal to the transmitter.

Abstract: A semiconductor device used as a semiconductor memory device is disclosed which is made of an amorphous silicon material that provides either a "1" or "0" memory state when the amorphous silicon material is in a non-conduction or insulating state and a "0" or "1" memory state when the amorphous silicon material is transformed, by use of a breakdown voltage applied to electrodes coupled thereto, into a conducting state. The amorphous silicon material is located adjacent to a doped semiconductor region of a semiconductor substrate separated only by a relatively thin primarily metal ohmic contact. The resulting semiconductor structure for the semiconductor device or semiconductor memory device is primarily a single level metalization type structure. A write-once, read-only semiconductor memory array is also disclosed which uses, as each memory cell of the array, one of the disclosed semiconductor memory devices.

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory with programmable EPROM configuration fuses located in a limited number of addresses of the on-chip program memory, the condition of each of EPROM fuse being defined as blown or not blown according to the value of the bit stored in the respective address of the on-chip program memory. The operating modes of the microcontroller are configurable by appropriately programming at least some of the EPROM fuses. Testing of the microcontroller in at least some of the operating modes is achieved by using latches outside the program memory to emulate the EPROM fuses, while suppressing the capability to set the condition of the EPROM fuses during the testing. Upon completion of the testing, control of the operating modes of the microcontroller is returned to the EPROM fuses, and the latches are precluded from further emulating the EPROM fuses.

Abstract: A microcontroller is adapted, when operating, to execute programs and instructions and, in response, to generate control signals to selectively control external apparatus. The microcontroller includes a power supply for supplying power to the overall device within a predetermined range suitable for its operation, and a clock for supplying a clock frequency to the microcontroller with a stability suitable for precise timing and counting within the device. The microcontroller is selectively reset to prevent it from executing programs and instructions for purposes of generating the control signals, and is maintained in the reset condition despite initiation of a removal from the reset condition, until the power supplied by the power supply is in a predetermined range and the clock frequency supplied by the clock is stable. In this way, no execution by the microcontroller is permitted until device stability is achieved, to prevent errors in execution.

Abstract: A microcontroller fabricated on a semiconductor chip has an on-chip EPROM program memory. The microcontroller is selectively configurable to operate in any one of a plurality of predetermined operating modes, including at least one secure microcontroller mode. A plurality of EPROM configuration fuses used for configuring the microcontroller and protecting its program memory from read, verify or write through any instruction initiated from other than a predetermined secure area of the chip, are mapped into the on-chip EPROM program memory as bits in respective address locations thereof. The value of a bit representing any one of said fuses is effective to determine the condition of the respective fuse. That condition is observed by reading the value of the respective bit for that fuse stored in the EPROM program memory.