Patents Assigned to Microchip Technology, Inc.
  • Patent number: 11398291
    Abstract: A method and apparatus for determining when actual wear of a flash memory device differs from a reliability state. Configuration files of a reliability-state classification neural network model are stored. The operation of a flash memory device is monitored to identify current physical characteristic values. A read of the flash memory device is performed to determine a number of errors. A neural network operation is performed using as input a set of threshold voltage shift offset values currently being used to perform reads of the flash memory device and the calculated number of errors, to identify a predicted reliability state. The identified current physical characteristic values are compared to corresponding tags associated with the predicted reliability state and a flag or other indication is stored when the comparison indicates that the identified current physical characteristic values do not correspond to the respective tags associated with the predicted reliability state.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: July 26, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Lorenzo Zuolo, Rino Micheloni
  • Patent number: 11392385
    Abstract: A system and method for monitoring processors operating in lockstep to detect mismatches in pending pipelined instructions being executed by the processors. A lockstep monitor implemented in hardware is provided to detect the mismatches in the pending pipelined instructions executing on the lockstep processors and to initiate an auto-recovery operation at the processors if a mismatch is detected.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 19, 2022
    Assignee: Microchip Technology Inc.
    Inventor: Pierre Selwan
  • Publication number: 20220188604
    Abstract: A method for performing a neural network operation includes receiving weight and bias values of a deep neural network (DNN). An array of feature values, a bias value and a set of weight values for a single layer of the DNN are coupled to a neural network engine. Multiply-and-accumulate operations are performed on the single layer at one or more multiply and accumulate circuit (MAC) to obtain a sum corresponding to each neuron in the single layer. A layer output value corresponding to each neuron in the single layer is coupled to a corresponding input of the MAC. The coupling a bias value and a set of weight values, the performing multiply-and-accumulate operations and the coupling a layer output value are repeated to generate an output-layer-sum corresponding to each output-layer neuron and an activation function is performed on each output-layer-sum to generate DNN output values.
    Type: Application
    Filed: June 14, 2021
    Publication date: June 16, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Lorenzo Zuolo, Rino Micheloni
  • Publication number: 20220191144
    Abstract: A network switch and associated method of operation for establishing a low latency transmission path through the network which bypasses the packet queue and scheduler of the switch fabric. The network switch transmits each of a plurality of data packets to the identified destination egress port over the low latency transmission if the data packet is identified to be transmitted over the low latency transmission path from the ingress port to the destination egress port, and transmits the data packet to the destination egress port through the packet queue and scheduler if the data packet is not identified to be transmitted over the low latency transmission path from the ingress port to the destination egress ports.
    Type: Application
    Filed: July 23, 2021
    Publication date: June 16, 2022
    Applicant: Microchip Technology Inc.
    Inventor: Morten Terstrup
  • Patent number: 11355187
    Abstract: A method for erasing a ReRAM memory cell that includes a ReRAM device having a select circuit with two series-connected select transistors. The method includes determining if the ReRAM cell is selected for erasing. If the ReRAM cell is selected for erasing, the bit line node is biased at a first voltage potential, the source line node is biased at a second voltage potential greater than the first voltage potential and the gates of the series-connected select transistors are supplied with positive voltage pulses. The difference between the first voltage potential and the second voltage potential is sufficient to erase the ReRAM device in the ReRAM cell. If the ReRAM cell is unselected for erasing, the gate of the one of the series-connected select transistors having its drain connected to an electrode of the ReRAM device is supplied with a voltage potential insufficient to turn it on.
    Type: Grant
    Filed: January 2, 2021
    Date of Patent: June 7, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Victor Nguyen, Fethi Dhaoui, John L McCollum, Fengliang Xue
  • Publication number: 20220165348
    Abstract: A method and apparatus for determining when actual wear of a flash memory device differs from a reliability state. Configuration files of a reliability-state classification neural network model are stored. The operation of a flash memory device is monitored to identify current physical characteristic values. A read of the flash memory device is performed to determine a number of errors. A neural network operation is performed using as input a set of threshold voltage shift offset values currently being used to perform reads of the flash memory device and the calculated number of errors, to identify a predicted reliability state. The identified current physical characteristic values are compared to corresponding tags associated with the predicted reliability state and a flag or other indication is stored when the comparison indicates that the identified current physical characteristic values do not correspond to the respective tags associated with the predicted reliability state.
    Type: Application
    Filed: March 26, 2021
    Publication date: May 26, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Lorenzo Zuolo, Rino Micheloni
  • Patent number: 11341304
    Abstract: A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: May 24, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Madhusudan Raman, Nizar Abdallah, Julien G. Dunoyer
  • Publication number: 20220136869
    Abstract: A redundant angular position sensor comprising a first angular position sensor including a first excitation coil, a first sensing coil and a second sensing coil and a second angular position sensor. The second angular position sensor including a second excitation coil, a third sensing coil and a fourth sensing coil. Each of the first, second, third and fourth sensing coils comprising a respective clockwise winding portion and a respective counter-clockwise winding portion. The redundant angular position sensor further comprises a rotatable inductive coupling element positioned in overlying relation to the sensing coils and separated from the sensing coils by a gap, wherein the rotatable inductive coupling element comprises four, substantially evenly radially spaced, sector apertures.
    Type: Application
    Filed: January 12, 2021
    Publication date: May 5, 2022
    Applicant: Microchip Technology Inc.
    Inventor: Ganesh Shaga
  • Patent number: 11323123
    Abstract: A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when a rollover event of a phase interpolator has occurred, and a correction circuit that adds a signed predistortion correction to a VCO clock cycle phase fraction value when the rollover detector circuit has detected the interpolator rollover event.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Microchip Technology Inc.
    Inventor: Mike Willingham
  • Patent number: 11313702
    Abstract: A system and method for monitoring analog front-end (AFE) circuitry of an inductive position sensor. A redundant AFE channel is provided and alternatively utilized with a sine AFE channel or a cosine AFE channel of the AFE circuitry to obtain a voltage difference that may result in a detection angle error at the electronic control unit (ECU) of the inductive position sensor.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 26, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Stephane Le Goff, Mathieu Sureau, Jebas Paul Daniel T, Naveen Cannankurichi, Subhasis Sasmal, Sunny Joel
  • Publication number: 20220115282
    Abstract: A method for forming a packaged electronic die includes forming a plurality of bonding pads on a device wafer. A photoresist layer is deposited over the device wafer and is patterned so as to form a photoresist frame that completely surrounds a device formed on the device wafer. Conductive balls are deposited over the bonding pads. The wafer is cut to form the electronic die and the electronic die is placed over the substrate. The conductive balls are heated and compressed, moving the electronic die closer to the substrate such that the photoresist frame is in direct contact with the substrate or with a landing pad formed on the substrate. Encapsulant material is deposited such that the encapsulant material covers the electronic die and the substrate. The encapsulant material is cured so as to encapsulate the electronic die. The substrate is cut to separate the packaged electronic die.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Matthias Klein, Andreas Zakrzewski, Richard Gruenwald
  • Publication number: 20220093397
    Abstract: A silicon carbide semiconductor device includes a silicon carbide (SiC) substrate having a SiC epitaxial layer disposed over a surface of the SiC substrate, the SiC substrate having a first conductivity and the SiC epitaxial layer having the first conductivity. A contact region and a well region are formed in the SiC epitaxial layer, the contact region and the well region have a doping level of a second conductivity opposite the first conductivity. The contact region lies completely within the well region, is not in contact with a region having the first conductivity and has edges recessed from edges of the well region.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Amaury Gendron-Hansen, Bruce Odekirk
  • Patent number: 11271712
    Abstract: A PHY chip for a synchronous Ethernet system includes N network input/output (I/O) ports, a first external recovered clock input, a first recovered clock output, and a first clock multiplexer having a plurality of data inputs, a select input, and an output coupled to the first recovered clock output, at least one of the data inputs coupled to a first recovered clock from a respective one of the N network I/O ports, a first additional data input coupled to the first external recovered clock input.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: March 8, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Thomas Joergensen, Brian Branscomb
  • Publication number: 20220058488
    Abstract: A method includes storing configuration files of a Multi-Core Neural Network Inference (MCNNI) model having Independent Categorized-Core-Portions (ICCP's). Each ICCP corresponds to one of a plurality of categories for each parameter. A first plurality of weighting values on each row of the weighting matrix of the MCNNI model have a nonzero value and a second plurality of weighting values on each row having a value of zero. The configuration files are loaded into a neural network engine. The operation of the integrated circuit device is monitored to identify a usage value corresponding to each of the parameters. A single neural network operation is performed using the usage values as input to generate, at the output neurons of each ICCP, output values indicating an estimation of one or more variable. The output values of the ICCP that corresponds to the input usage values are identified and are sent as output.
    Type: Application
    Filed: January 13, 2021
    Publication date: February 24, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Lorenzo Zuolo, Rino Micheloni
  • Patent number: 11257734
    Abstract: A thermal management package for a semiconductor device includes a high dielectric constant material substrate, a high thermal conductivity slug disposed in a first window in the high dielectric constant material substrate and held therein by a first bonding material, an outer substrate formed from a material having a low dielectric constant and having a second window formed therein, the high dielectric constant material substrate disposed in the second window in the low dielectric constant outer substrate and held therein by a second bonding material.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: February 22, 2022
    Assignee: Microchip Technology Inc.
    Inventor: Damian McCann
  • Patent number: 11244876
    Abstract: A packaged electronic die having a micro-cavity and a method for forming a packaged electronic die. The packaged electronic die includes a photoresist frame secured to the electronic die and extending completely around the device. The photoresist frame is further secured to a first major surface of a substrate so as to form an enclosure around the device. Encapsulant material extends over the electronic die and around the sides of the electronic die. The encapsulant material is in contact with the first major surface of the substrate around the entire periphery of the electronic die so as to form a seal around the electronic die.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: February 8, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Matthias Klein, Andreas Zakrzewski, Richard Gruenwald
  • Patent number: 11245391
    Abstract: Described herein are multiple designs for an improved analog switch for use in transmitting high voltage signals without using high voltage power supplies for the switch. The analog switches are able to pass and block input signals in the approximate range of ?100 V to +100 V. The use of translinear loops and a bootstrap configuration results in a constant on-resistance of the symmetrical switches and matches the conductance of each analog switch to the transconductance of an NMOS transistor, which can be easily stabilized with a constant gm biasing scheme. In certain embodiments, a shunt termination (T-switch) configuration is used for better off-isolation, and each of the symmetrical switches has its own translinear loop and thus flexibility of on-resistance and termination voltage.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: February 8, 2022
    Assignee: MICROCHIP TECHNOLOGY INC.
    Inventors: Isaac Ko, Ka Wai Ho, Wan Tim Chan, Jimes Lei
  • Publication number: 20220034684
    Abstract: A system and method for monitoring analog front-end (AFE) circuitry of an inductive position sensor. A redundant AFE channel is provided and alternatively utilized with a sine AFE channel or a cosine AFE channel of the AFE circuitry to obtain a voltage difference that may result in a detection angle error at the electronic control unit (ECU) of the inductive position sensor.
    Type: Application
    Filed: October 20, 2020
    Publication date: February 3, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Stephane Le Goff, Mathieu Sureau, Jebas Paul Daniel T, Naveen Cannankurichi, Subhasis Sasmal, Sunny Joel
  • Publication number: 20220029778
    Abstract: System and method for synchronizing a plurality of nodes to a timing signal using a daisy-chain network having a forward transmission path and a reverse transmission path connected at a midpoint. Latency of the timing signal to the midpoint of the daisy-chain network is determined, a respective latency of the timing signal from the node to the midpoint of the daisy-chain network is determined, and a respective timing offset for each of the plurality of nodes is calculated. A local time-of-day counter at each of the plurality of nodes is adjusted based upon the respective timing offset of the node to synchronize the plurality of nodes to the timing signal.
    Type: Application
    Filed: April 28, 2021
    Publication date: January 27, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Atanu Chattopadhyay, Andras de Koos
  • Publication number: 20220027083
    Abstract: A method and apparatus for reading a flash memory device are disclosed. A Regression Neural Network (RNN) inference model is stored on a flash controller. The RNN inference model is configured for identifying at least one Threshold-Voltage-Shift Read-Error (TVS-RE) curve that identifies a number of errors as a function of Threshold Voltage Shift Offset (TVSO) values. The operation of a flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic values. The input for the neural network operation includes the usage characteristic values. A TVSO value is identified corresponding to a minimum value of the TVS-RE curve. A read of the flash memory device is performed using a threshold-voltage-shift read at the TVSO value.
    Type: Application
    Filed: November 5, 2020
    Publication date: January 27, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Lorenzo Zuolo, Rino Micheloni