Abstract: A remote control system for opening and closing a barrier, such as a garage door, includes an RF receiver and a plurality of RF transmitters. The transmitters and receiver include circuitry programmed to provide transmission of encrypted code signals each time the transmitters are used and employing a code hopping method which prevents unauthorized signal interception or code “grabbing”. The system is operated in a code learning mode for the receiver by momentarily actuating a receiver learn mode button for receiving each transmitter identification code and a secret decryption key for that transmitter with the system automatically returning to the operate mode. Each transmitter identification and secret key code signal is automatically and randomly stored in an available and unused memory in the receiver circuitry.

Abstract: An output buffer, a slew-rate control circuit, a break-before-make circuit, and a current limited input amplifier are connected as a digital output driver. This provides a simple apparatus and method of switching current control and slew-rate control that limits power consumption of the digital output driver. To further minimize switching current, capacitors may be added to the break-before-make circuit. A comparator input circuit may be connected to the current limited input amplifier to form a comparator having a low-power-consuming digital output.

Abstract: A terminal assembly for measuring electrical current passing to and from a battery post, including an electrically conductive collar for connecting to a post of a battery, and an electrically conductive terminal for receiving a connector of a load. An electrically conductive resistor having a known resistance extends between outer surfaces of the collar and the terminal. The terminal assembly is incorporated into a battery, which also includes a volt meter connected between the outer surfaces of the collar and the terminal for measuring the voltage drop across the resistor, memory for storing the known resistance of the resistor, and a processor programmed to receive the measured voltage drop from the volt meter, retrieve the known resistance from the memory, and calculate current flow through the resistor based on the measured voltage drop and the known resistance, whereby current flow to and from the battery can be measured.

Abstract: A spectrum analyzer that may be implemented by a simple microcontroller that does not have a hardware multiply function is disclosed. The spectrum analyzer of the present invention utilizes at least five frequency bins. The input signal is sampled at four times the bin frequency. The input signal is sampled at twice the Nyquist rate, which results in symmetries in the sin(wn) and cos(wn) functions. These symmetries allow the in-phase and quadrature components of the input signal to be calculated by add, ignore or subtract operations instead of the more complex multiplication and integration operations. Accordingly, the energy for each bin may be calculated with a minimum number of multiply operations. Because the number of multiply operations have been significantly reduced, these multiply operations may be performed by software instead of hardware. As a result, the spectrum analyzer may be implemented with a simple processor that does not have a hardware multiply.

Abstract: An apparatus for measuring electrical energy passing to and from a battery post. The apparatus includes a resistor having a known resistance, a first conducting surface and a second conducting surface. The conducting surfaces are arranged such that current flow from a battery post will travel through the resistor from the first conducting surface to the second conducting surface, and current flow to the post travels through the resistor from the second to the first conducting surfaces. The energy measuring apparatus further includes a first lead electrically connected to the first conducting surface of the resistor, and a second lead electrically connected to the second conducting surface of the resistor.

Abstract: A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor.

Abstract: Several calibration techniques for a precision relaxation oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature. The calibration techniques provide for different methods of determining CTAT current, PTAT current or the ratio of PTAT current to CTAT current. The calibration techniques provide different methods for determining CTAT and PTAT calibration values and for setting CTAT and PTAT calibration select switches.

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Abstract: A method and system for the remote control of devices having a secure self learn capability. The system includes an encoder and a decoder, the encoder encoding variable information including a user key using a non-linear algorithm to produce an encoded value transmitted to the decoder, the decoder decoding the value using the same algorithm. In a learning mode a new encoder is to be added to the system. The new encoder produces an encoded value using a key generation seed. The decoder, upon receiving the encoded key generation seed, produces a decoding key based upon the decoded key generation seed. The decoding key is stored in the decoder memory allowing valid recognition of the new encoder in a secure manner.

Abstract: A loadable counter circuit which is able to perform multiple contiguous counts. The loadable counter circuit uses a counter for monitoring a number of specified events. A data storage device is coupled to the counter for loading the counter with counter values for each of the contiguous counts. A control logic circuit is coupled to the counter and to the data storage circuit for loading the counter and the data storage device with the counter values.

Abstract: An integrated circuit having a microcontroller, mask programmed read only memory, functions such as clock oscillator, analog-to-digital converter, timers, etc., where each may be adjusted with a digital input to a desired calibration value. The digital input resulting in the desired calibration value being stored in a programmable fuse array.

Abstract: A remote control system for opening and closing a barrier, such as a garage door, includes an RF receiver and a plurality of RF transmitters. The transmitters and receiver include circuitry programmed to provide transmission of encrypted code signals each time the transmitters are used and employing a code hopping method which prevents unauthorized signal interception or code "grabbing". The system is operated in a code learning mode for the receiver by momentarily actuating a receiver learn mode button for receiving each transmitter identification code and a secret decryption key for that transmitter with the system automatically returning to the operate mode. Each transmitter identification and secret key code signal is automatically and randomly stored in an available and unused memory in the receiver circuitry.

Abstract: A precision relaxation oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature. The invention has a oscillation generator and two independent current generators. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current which is independent of temperature. The precision relaxation oscillator with temperature compensation is implemented on a single, monolithic integrated circuit.

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

Abstract: According to the present invention, there is provided an integrated circuit useful in an electronic encoding device having a voltage source, a user interface and a transmitter. In one embodiment the integrated circuit includes a wake-up circuit which generates a signal responsive to an input received from the user interface; power switching logic which provides power from the voltage source to a non-regulated power bus and a voltage regulating circuit, the power switching logic being responsive to the signal from the wake-up circuit; a regulated power bus in communication with the voltage regulating circuit; non-volatile memory in communication with the regulated power bus; encoder logic in communication with the regulated power bus, the encoder logic having output logic which provides a signal to the transmitter.

Abstract: A microcontroller for use in battery charging and monitoring applications is disclosed. The microcontroller includes a microprocessor and various front-end analog circuitry including a slope A/D converter and a multiplexer for allowing a plurality of analog input signals to be converted to corresponding digital counts indicative of signal level. The microcontroller further includes an on-chip temperature sensor, used in conjunction with the A/D converter, to monitor the temperature of the microcontroller. The temperature sensor generates and uses a differential voltage that is obtained across the base-emitter functions of two compatible bipolar transistors having dissimilar emitter areas. This differential voltage is proportional to temperature and may be sampled by the A/D converter to obtain a digital count indicative of the temperature of the microcontroller.

Abstract: A microcontroller chip with a central processing unit (CPU) is adapted to control an external system with which the device is to be installed in circuit. The microcontroller chip includes an on-chip peripheral universal timing function module with a register for storing a value selected to signify a distinctive event in a waveform. A timer generates a series of values as a function of time as a measure of the value selected to signify the distinctive event. The register and the timer are coupled to a pin of the microcontroller chip on which said waveform is to be applied. Equality between the values in the timer and the register signify the distinctive event as one of a capture and a compare of an event in the waveform, to generate an interrupt to the CPU.

Abstract: An oscillator circuit (30, 40) for starting-up and operating at low voltages has been provided. The oscillator circuit includes an inverter circuit(31, 41) coupled across first and second terminals of a resonant circuit (14). The inverter circuit includes a push-pull driver stage having a P-channel transistor (18) and an N-channel transistor (20). The common drain electrodes of each are coupled to the second terminal of the resonant circuit. The source electrodes of the P- and N-channel transistors are respectively coupled to first and second supply voltage terminals. The gate electrode of the first transistor is coupled to the first terminal of resonant circuit. The inverter circuit further includes a circuit (32, 42) for shifting the voltage level applied to the gate electrode of the second transistor, relative to the voltage applied to the gate electrode of the first transistor, by a predetermined voltage.

Abstract: An I.sup.2 C bus-compatible, serial EEPROM device is used in applications involving storage and serial transmission of configuration and control information for an intelligent peripheral device with which the EEPROM device is associated, for communication on a bus to a host device adapted to control the peripheral device. The EEPROM device has a memory array for storing data representing the configuration and control information. Two modes of data transmission are supported by the EEPROM device, and are alternately and selectively established according to whether data stored in the EEPROM array is to be read only, by sequential output onto the bus, or the array is also to be allowed to be written to. The arrangement ultimately allows intelligent interaction between the host device and the peripheral device. A separate clock line supplements the usual clock line and data line of an I.sup.2 C bus to support the distinct and different modes, with clocking by the respective clock line for the established mode.

Abstract: A semiconductor device used as a semiconductor memory device is disclosed which is made of an amorphous silicon material that provides either a "1" or "0" memory state when the amorphous silicon material is in a non-conduction or insulating state and a "0" or "1" memory state when the amorphous silicon material is transformed, by use of a breakdown voltage applied to electrodes coupled thereto, into a conducting state. The amorphous silicon material is located adjacent to a doped semiconductor region of a semiconductor substrate separated only by a relatively thin primarily metal ohmic contact. The resulting semiconductor structure for the semiconductor device or semiconductor memory device is primarily a single level metalization type structure. A write-once, read-only semiconductor memory array is also disclosed which uses, as each memory cell of the array, one of the disclosed semiconductor memory devices.