Abstract: A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.

Abstract: With respect to input/output requests; a microprogram controls collection of data according to the data format; data accessing divides the requests for every recording medium and performs asynchronous processing; an on-line process is carried out in view of the processing priority order of the requests; parallel accessing sets requests for each medium; buffer control assures a block buffer and a page address list before receiving requests; data accessing sets a list of CCHHR codes in response to a continuous characteristic of the stored state in the recording medium; and mode deciding judges the two data transfer modes, a page search mode and a data search mode, in response to the requests.

Abstract: An input/output control apparatus connected to a plurality of input/output units such as disc systems and an input/output control method. A cache memory is divided into a plurality of storage areas for data management. Data stored in the disc systems are stored in the storage areas. In response to an output request from a HOST system to the disc systems, data outputted from the latter are stored in the storage areas of the cache memory. The data stored in the storage areas and outputted therefrom in response to the output request are transferred to the disc systems. The storage areas storing the data requested and not yet stored in the disc systems are grouped correspondingly to the disc systems where the output data are to be stored. The resulting group is managed as a first attribute group. Write-after processing for every disc units can be executed in parallel efficiently without involving high processing overhead.

Abstract: In a control unit having a external storage device, a method for selecting a loading method of data stored in the cache memory into the cache memory in accordance with an access pattern to the data, and an apparatus therefor are disclosed. The selection of the loading method is selection of control mode or procedure in accordance with the loading method, and it is attained by a learn function.

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: A digital timer unit employs a capture register and a save register. The capture register latches count data provided from a counter in accordance with a first edge of an event pulse. The save register latches count data of the capture register in accordance with a second edge of the event pulse while the capture register latches new count data provided from the timer. Data within the capture register and the save register after completion of the event pulse define a duration of an event pulse with a relatively small duration.

Abstract: A computer aided text generation system and method provides functions of aiding a logical outline structure of a text, aiding the text generation using a conventional expression, aiding the text generation without using conventional expression, aiding the refinement of the generated text and aiding the collection of illustrative sentences. The present system permits generation of a finished text of high quality.

Abstract: A switching system is provided in which when a calling subscriber has transmitted an identification (ID) number of a called subscriber and an ID number of the calling subscriber from a calling terminal to a switching equipment having a subscriber control table at the time of making a call, the switching equipment receives the ID numbers and connects the calling terminal with the called terminal.

Abstract: When a coprocessor communicates a plurality of data items with a master processor and a memory according to a bus access cycle activated by the master processor, the coprocessor is supplied therein with information indicating a data storage position as a data transfer source or destination. The master processor and coprocessor independently monitor the number of the sequence of data transfers or the end of the sequence of data transfer operations. As a consequence, when executing a sequence of plural data transfer operations, the coprocessor need not receive a command from the master processor for each data transfer thereto. Further, it is not required for the coprocessor to indicate the end of the sequence of data transfer cycles to the master processor since the master processor can determine this on its own.

Abstract: An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.

Abstract: A method for searching the memory of a data processing apparatus including a decoder for decoding the contents of an instruction and an execution unit for executing is performed in response to an instruction based on an output from the decoder, the search instruction which identifies a desired data storage area from a plurality of data storage areas in the memory which includes an array data structure.

Abstract: A graphic processor comprises an input device for inputting a command from an operator, a display device for displaying graphic data and a computer for preparing and correcting graphic data by a command input from the operator and for making display control of the display device. When the operator wants to know the content of the command that is executed, he instructs the command to the computer. A command name, a processing content and a figure as an object of processing are calculated from history data instructed from the computer. The figure as the object of processing, the command processing content and the relation of correspondence are symbolized and displayed on the display device. Furthermore, a parametric figure is also displayed visually on the display device.

Abstract: A semiconductor memory device is provided which includes a plurality of memory arrays each including main word lines, sub word lines to which a plurality of memory cells are connected, and a decoder which selectively connects the sub word lines to the main word lines. The main word lines are relatively short, since they are isolated electrically between memory arrays, and their resistance can thus be relatively low. The main word lines are not directly connected with a plurality of memory cells, and this results in a smaller capacitance coupled to the main word lines than is customarily the case. Consequently, the semiconductor memory device can have an enhanced operating speed.

Abstract: A storage control apparatus contains plural request stacks for storing the access request; a stack selecting circuit for selecting a request stack by accepting the access requests one after another and for storing the access request; and a priority determining circuit for selecting the access request stored in said request stack in order of priority and makes access to a main storage unit in response to an access request from an input-output processor, instruction processor and the like. When memory access requests are issued continuously from the unit as a source of issuing the same access request to the storage control apparatus, the access request which follows can make access to a cache memory while the previous request is making access to the main storage unit, thereby preventing a reduction in a total throughput.

Abstract: A data processing system which encludes an instruction processor, a storage controller, a main storage, and an extended storage. The storage controller contains a data transfer unit for transferring data between the main storage and the extended storage by an instruction from the instruction process specifying an amount of the data to be transferred. The data transfer unit is provided in the storage controller and with a data buffer and an address addition-subtraction circuit for operating a source address and a destination address. The data is transferred between the main storage and the extended storage by sending to a firmware of a storage control a main storage real address translated from a main storage virtual address specified by the instruction, the number of data to be transferred from the main storage, an extended storage real address, and the number of bytes to be transferred from the extended storage, in a manner so as to match with a unit of data to be processed on the extended storage.

Abstract: A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.

Abstract: In a microprocessor, a minimum instruction code length is set to a predetermined number of bits (e.g. one byte) length. One feature of the invention is that an instruction set which can selectively expand the instruction code length at a unit of the predetermined number of bits is used. Another feature is that an operand addressing mode and a type of operation for an operand are designated by separate predetermined number of code bits which are coded in a common coding scheme so that an instruction decoder is shared by those codes.

Abstract: In one aspect of correcting phase distortion in an MR imaging system at high speed and with high precision, partial regions having any shapes are established on a complex image reconstruction, linear phase distortion is estimated for every partial region and the phase distortion of the whole image is corrected by use of the estimated phase distortion. In another aspect, a plurality of phase distortion patterns are measured in advance through phantom imaging and stored. The phase distortion pattern is invariable and hence it is not necessary to perform the measurement for each impage processed. Phase distortion included in data acquired through imaging is corrected by representing it as a summation of the plurality of phase distortion patterns with weighting factors.

Abstract: In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet.

Abstract: In a static type RAM, a sense amplifier includes first and second dissymmetric type differential amplifier circuits each of which has a pair of differential transistors and an active load circuit such as a current mirror circuit connected to the drains of the differential transistors. One of balanced signals delivered from a memory cell is supplied to the non-inverting input terminal of the first dissymmetric type differential amplifier circuit and the inverting input terminal of the second dissymmetric type differential amplifier circuit. The other of said balanced signals is applied to the remaining input terminals of the first and second dissymmetric type differential amplifier circuits. As a result, notwithstanding that balanced signals cannot be delivered from each dissymmetric type differential amplifier circuit, amplified balanced signals can be obtained.