Abstract: Herein disclosed is a semiconductor device including a plurality of IIL elements which are electrically connected by a plurality of first wirings arranged generally parallel with one another and a plurality of second wirings arranged generally parallel with one another and extended in different direction to the first wirings.

Abstract: A data converting system converts CRT display data into display data for another display unit such as a liquid crystal display unit by use of a memory. The system includes a data load controller which selects one segment of data out of two segments of data in the CRT display data successively while changing the segment position to be selected alternately in every two frame scanning periods so that the CRT display data for one complete picture is written into the memory in two frame scanning periods, i.e., a segment is written into the memory once for every two adjacent segments. Display data is read out of the memory in the data form conformable to the other display unit.

Abstract: A semiconductor memory includes a dummy cell for forming a reference potential, a read-only memory cell, and a differential amplifier circuit which receives the reference potential formed by the dummy cell and a signal read out from the memory cell. The differential amplifier circuit is dynamically operated so that the semiconductor memory is made smaller in power consumption and size than conventional units. Moreover, in order to reduce the power consumption, the memory cell is brought into the nonselection state when a predetermined time has passed after being selected. In addition, the semiconductor memory is provided with a compensating circuit in order to make the value of the capacitance connected to a word line for transmitting a selecting signal to the memory cell and the value of the capacitance connected to a dummy word line for transmitting a selecting signal to the dummy cell substantially equal to each other.

Abstract: Disclosed are memory cells of a vertical-type read only memory (ROM) having a plurality of MISFETs connected in series. The MISFETs include gate electrodes formed with multiple conductive layers, in which some of the MISFETs are set to the depletion type and at least some of the remaining MISFETs are set to the enhancement type, so as to write information in the memory cells. The information write operation is conducted through at least two steps. Namely, in the first information write step, gate electrodes are used as a mask to implant an impurity; and in the second step, an impurity is implanted through the gate electrodes into the surface of the semiconductor substrate. These steps enable a semiconductor memory device, such as a vertical-type mask ROM having memory cells with a reduced series resistance and being suitable for a high degree of integration, to be produced.

Abstract: In an analysis processor which utilizes a parameter table for setting a processing condition and analyzes data in accordance with the content of table, a process for registering/correcting the parameter table is standarized for various analysis processing programs so that each of the analysis processing programs is divided into an analysis processing procedure instruction section and a parameter table section. Thus, a plurality of different analysis process can be performed in one analysis processor. Any table in the analysis processing programs may be readily referred to by an instruction through a keyboard of the analysis processor and may be registered and corrected. Thus, a user can alter the analysis processing program as he/she desires.

Abstract: In a resin packaged semiconductor device including a semiconductor element, the back side of which is bonded to a support and the front side of which has electrodes which are electrically connected to electroconductive portions by fine leads, when an adhesive composition comprising an epoxy resin, a novolak type phenolic resin, a solvent for the both resins and a powdery filler, and if necessary, a curing accelerator and a coupling agent, is used for binding the semiconductor and the support, the resulting semiconductor device is excellent in moisture resistance and corrosion resistance.

Abstract: Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

Abstract: In a one-chip microcomputer, a EPROM is formed together with a ROM and RAM on one semiconductor substrate. Data such as fixed data necessary in the microcomputer can be changed by the use of the EPROM. In case data are to be written in the EPROM, a EPROM writer is used. This EPROM writer outputs write data to the EPROM and checks (or verifies) the data written in the EPROM immediately thereafter. If any error is detected, the subsequent data write is interrupted. In order to inhibit the unnecessary operation interruption in case the address designated by the EPROM writer comes out of the range of the EPROM, the checking (or verifying) data signal to be fed from the one-chip microcomputer to the EPROM writer is forcibly set at a level which indicates satisfactory operation of the EPROM.

Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

Abstract: A semiconductor integrated circuit device incorporating bipolar transistors and IILs comprises respective buried layers in a substrate and active regions. A buried layer formed in the IIL region has a larger Gummel number than that of a buried layer formed in the bipolar transistor region so that a leakage current to the substrate is prevented. A larger Gummel number of the buried layer is accomplished by increasing the impurity concentration or the thickness of the layer. The device structure allows an enhanced circuit packing density, while suppressing a leakage current to the substrate.

Abstract: A semiconductor integrated circuit device includes a semiconductor nonvolatile memory, a booster circuit which generates a high voltage required for writing the data into the semiconductor nonvolatile memory, and a control circuit. With the thus constructed device, however, various external control signals often fail to assume definite levels when the power source is closed. If an operation mode to be designated is erroneously determined to be a write operation mode due to obscure levels of the external control signals, then the write operation is executed erroneously. To prevent such an erroneous operation from developing when the power source is closed, provision is made of a power source closure detector circuit and a suitable gate circuit. Owing to these circuits, the output of the booster circuit is being applied to the memory element from the time from when the power source circuit is closed up to the times when the read operation mode is designated by an external control signal.

Abstract: Disclosed is a semiconductor integrated circuit device comprising a protective circuit including a MOSFET which is connected directly to a bonding pad and which is connected in the form of a diode, and a resistor which is connected to the bonding pad at a stage posterior to the MOSFET. A drain region of the MOSFET is connected to the bonding pad, and has a large area of at least a certain fixed value in order to raise a voltage at which a P-N junction is destroyed.

Abstract: A decoding circuit is operative to decode a differential Manchester code consisting of four symbols "J", "K", "1" and "0" each composed of two consecutive signal elements. For detection of the symbol "J" and consequent determination of the symbol boundary, the decoding circuit has a circuit configuration which takes advantage of the fact that the symbol "K" immediately follows the symbol "J" and three consecutive signal elements, two of which are included in the symbol "J" and one of which is for a symbol immediately preceding the symbol "J", have the same polarity. To prevent an error that a second occurrence of the symbol "J" is detected after completion of detection of the symbol "J", the decoding circuit has an additional circuit configuration which inhibits the detection of the symbol "J" until the symbol "0" or the symbol "1", for example, is detected.

Abstract: Herein disclosed is a DRAM which has such a carrier trapping region around a memory cell array as can trap minority carriers deep in a semiconductor substrate so that the minority carriers to be generated in the semiconductor substrate by alpha rays may be sufficiently trapped. The memory cell of the DRAM has a capacitor which is partially formed of the semiconductor substrate. The carrier trapping region is formed by making use of trenches or a well region.

Abstract: A sign generation system having a plurality of carry save adders. When adding a sum and a carry generated by a carry save adder in a next stage carry save adder, a full sum of two-bit sign fields adjacent to data fields of the sum and the carry is calculated.The resulting two-bit sign is combined with a constant to generate an exact sign, decreasing number of transferred sign bits.

Abstract: A reliability analyzing system for manufacturing processes is disclosed, which comprises a computer system provided with a data memory device, a central processing device and input/output devices, terminals which input/output information into/from said computer system, and output devices for manufacturing sites; whereby said data memory device stores required specifications for each product, works for manufacturing and controlling processes, information relating to items, such as required specifications, works, control items, etc. and information mutually relating different items, and on the basis of the stored information, reliability analysis for each process is effected for all the processes and reliability analysis for each required specification is performed for all the required specifications.

Abstract: A protective cover for photoprinting system comprises a cover portion made of a transparent thin plate of inorganic material, an antireflection multiple coating provided on at least one of the inner and outer surfaces of the cover plate, and a spacer arranged on the peripheral portion of the cover plate for keeping the inner surface of the cover plate away from the surface to be protected, e.g., pattern surface of photomask and sealing the space between them.Since the cover plate is made of inorganic material, the mechanical strength thereof is large. Since the cover plate is thin and the antireflection multiple coating is provided on the cover plate, absorption of light therein is little and confusion of the pattern image due to rays reflected by the boundaries of the cover plate is ignorable.

Abstract: This invention discloses a semiconductor device, and method of manufacturing such device, which provides a high degree of moistureproofing, provides a high production yield, and in which defective elements can be replaced by the use of fuses. A circuit test of the device is conducted while at least part of each of a fuse and a bonding pad is exposed through a first passivation film covering a semiconductor substrate on which circuit elements such as MISFETs and capacitors are formed, and any defective elements are replaced by the use of fuses. Contamination of and damage to the elements during the test can thus be prevented. Thereafter, a second passivation film is formed so as to cover all the essential portions of the fuses and bonding pads. The exposure of cracks in the fuses and bonding pads is thus prevented, and the invasion of moisture, etc., into the lower layers below the fuses and bonding pads is also prevented, thereby improving the moistureproofing and reliability of the device.

Abstract: A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO.sub.2 film and a thin Si.sub.3 N.sub.4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si.sub.3 N.sub.4 film.

Abstract: A memory device in accordance with the invention has an array of memory cells including a plurality of main memory cells which are adapted to be utilized by a user for storing information and a plurality of checking memory cells which store data placed therein at the time of manufacturing of the array which is read out to check a performance characteristic of the array of memory cells prior to the storing of data in the main memory cells. Addressing means are associated with the array of memory cells for permitting selective addressing of either the main memory cells or the checking memory cells within the array by the application of selected first or second signal levels to addressing lines coupled to the array. An output circuit is coupled to the array of memory cells for outputting data from within selected cells within the array in cooperation with the addressing circuit.