Abstract: A method for determining an initial rotor position of a permanent magnet synchronous motor (PMSM) includes: generating a plurality of transient currents by applying a plurality of voltages to each phase stator winding of a three phase stator winding of the PMSM; generating three phase current differences according to the plurality of transient currents; determining a first zone in which the initial rotor position of the PMSM is located according to the three phase current differences, wherein angles between 0-360 degrees are divided into a plurality of zones, and the first zone is selected from the plurality of zones; calculating three line current differences according to the three phase current differences; and determining the initial rotor position of the PMSM according to the first zone and the three line current differences.

Abstract: A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

Abstract: A comparator circuit with dynamic biasing comprises a comparator, first dynamic biasing generator, first extra biasing device, second dynamic biasing generator, and second extra biasing device. The comparator includes a biasing circuit, input stage, active loads, and output terminal. The input stage has a first input terminal, second input terminal, first current path, and second current path. The comparator is configured to output an output signal at the output terminal according to the first input signal and second input signal. The first dynamic biasing generator is coupled between a first detection node and the first extra biasing device coupled to the biasing circuit. The second dynamic biasing generator is coupled between a second detection node and the second extra biasing device coupled to the biasing circuit. The first and second detection nodes are between the input stage and the active loads.

Abstract: The present disclosure provides satellite tracking systems and tracking methods. The satellite tracking system includes an array of antenna elements and a control unit. A feed current for each of the antenna elements passes through a phase shifter. The control unit generates a control signal for the phase shifter. The satellite tracking system searches, positions, and tracks a target satellite in accordance with the control signal. The satellite tracking systems and methods utilize step scanning and particle swarm optimization in the search stage, compensating for gaps formed during the satellite searching in the positioning stage, and conical scanning in the tracking stage.

Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.

Abstract: A loudspeaker controller for estimating a fundamental resonance frequency of a loudspeaker includes: an amplifier circuit, arranged to generate a driving signal of the loudspeaker according to an audio input signal; a sensing circuit, arranged to sense characteristics of the driving signal to generate a measurement signal; a plurality of band pass filter circuits, arranged to filter the measurement signal to generate a plurality of filter outputs, respectively, wherein the plurality of band pass filter circuits have different passbands; and an estimation circuit, arranged to estimate the fundamental resonance frequency according to the plurality of filter outputs.

Abstract: A loudspeaker controller for estimating a fundamental resonance frequency of a loudspeaker includes: an amplifier circuit, arranged to generate a driving signal of the loudspeaker according to an audio input signal; a sensing circuit, arranged to sense characteristics of the driving signal to generate a measurement signal; a plurality of band pass filter circuits, arranged to filter the measurement signal to generate a plurality of filter outputs, respectively, wherein the plurality of band pass filter circuits have different passbands; and an estimation circuit, arranged to estimate the fundamental resonance frequency according to the plurality of filter outputs.

Abstract: A data control circuit includes a first latch circuit, a self-block circuit, a second latch circuit, a third latch circuit, a first data timing-labeled signal generating circuit, and a second data timing-labeled signal generating circuit. The first latch circuit is arranged to receive a data window signal. The self-block circuit is coupled to the first latch circuit, and is arranged to generate a protection signal. The second latch circuit is coupled to the self-block circuit, and is arranged to output a first data timing-labeled signal. The third latch circuit is coupled to the second latch circuit, and is arranged to generate a second data timing-labeled signal. The first data timing-labeled signal generating circuit is arranged to generate a third data timing-labeled signal. The second data timing-labeled signal generating circuit is arranged to generate a fourth data timing-labeled signal.

Abstract: A parametric equalizer includes an equalizer circuit, a first protection circuit, a second protection circuit, and a first addition circuit. The equalizer circuit is arranged to receive an input signal, and process the input signal to generate an output signal. The first protection circuit is arranged to generate a first protection signal according to the output signal, the input signal, and a first processed signal. The second protection circuit is arranged to generate a second protection signal according to the input signal and a second processed signal. The first addition circuit is coupled to the first protection circuit and the second protection circuit, and is arranged to combine the first protection signal and the second protection signal to generate an equalizer output signal.

Abstract: An amplifier with an input stage comprising: a first current mirror; a first input differential pair; a first current source; a second current source; a second input differential pair, wherein the first input differential pair and the second input differential pair receive a reference voltage; a second current mirror; and a voltage control transmission circuit. An extra current path in the first current mirror is formed and a current flowing through the extra current path flows through the second current mirror to a ground when the reference voltage is higher than a first predetermined value. Also, an extra current path in the second current mirror is formed and a current flowing through the extra current path in the second current mirror flows to the first current mirror when the reference voltage is lower than a second predetermined value.

Abstract: A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.

Abstract: A method for determining zero crossing occurrence in an alternating current (AC) signal with constant frequency of a permanent magnet synchronous motor (PMSM) includes: sampling the AC signal to obtain a plurality of data points; starting to count a number of consecutive data points that have sampled values with a same sign in a detection range, to generate a count value, wherein the consecutive data points are included in the plurality of data points; determining whether the count value is equal to a zero crossing determination value; and in response to the count value being equal to the zero crossing determination value, determining that a zero crossing occurs at a last data point of the consecutive data points.

Abstract: A parametric equalizer includes a first parametric equalizer circuit, a second parametric equalizer circuit, a first multiplication circuit, a second multiplication circuit, an addition circuit, and a weighting control circuit. The first parametric equalizer circuit processes an input signal to output a first output signal. The second parametric equalizer circuit processes the input signal to output a second output signal. The first multiplication circuit multiplies the first output signal and a first weighting value to generate a first adjusted output signal. The second multiplication circuit multiplies the second output signal and a second weighting value to generate a second adjusted output signal. The addition circuit combines the first adjusted output signal and the second adjusted output signal to generate an equalizer output signal. The weighting control circuit dynamically adjusts the first weighting value and the second weighting value according to the equalizer output signal.

Abstract: A post over-erase correction (POEC) method with an auto-adjusting verification mechanism and a leakage degree detection function detects gm degradation or leakage degree of flash cells before or after entering the POEC process. When a preset condition is satisfied, the auto-adjusting verification mechanism of the POEC is switched on to further reduce leakage current. After cycling, the POEC repairs Vt of over-erased cells to a higher level to solve leakage issues. The erase shot count increases due to slower erase speeds after cycling. Therefore, the cycling degree of flash cells is detected by observing the shot number that the erase operation used. When the leakage phenomenon becomes serious, the bit line (BL) leakage current, amount of repaired BLs, and over-erase correction (OEC) shot number will increase during the OEC procedure. Therefore, the leakage degree of flash cells can be detected by inspecting the above data.

Abstract: A direct current (DC) offset protection circuit includes: a DC offset detection circuit and a control circuit. The DC offset detection circuit is arranged to detect whether a DC component exists in pulse-width-modulation (PWM) signals and accordingly generate a DC offset detection result. The control circuit is arranged to control an audio system according to the DC offset detection result. The DC offset detection circuit comprises a PWM polarity judgment circuit, a cascaded integrator-comb (CIC) filter and a DC offset judgment circuit. The PWM polarity judgment circuit is arranged to judge a polarity of complementary PWM signals and accordingly generate a polarity indication value. The CIC filter is arranged to generate a filter output signal by averaging a plurality of polarity indication values. The DC offset judgment circuit is arranged to generate the DC offset detection result by comparing the filter output signal with a predetermined DC threshold.

Abstract: An erase voltage compensation mechanism for group erase mode with bit line leakage detection comprises performing a block erase operation by applying an erase voltage. Continue block erasing until bit line leakage is detected upon which the erase voltage is latched and over-erase correction is performed. A compensation voltage value is calculated by finding the difference between an upper bound of a threshold voltage distribution and an erase verify point when the bit line leakage was detected. The latched erase voltage is increased by the compensation voltage to create a compensated voltage. A group erase operation is performed and the group address is incremented by 1 and the compensated voltage value is loaded. Then the group erase operation is performed on the next group. The address is incremented, the compensated voltage is loaded, and the group erase operation is performed until the group is the last group.

Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

Abstract: A COT (constant on-time) buck converter includes a first transistor, a second transistor, a driver circuit, an inductor, a first resistor, a second resistor, a capacitor, a load, and a feedback loop circuit. The feedback loop circuit includes a first switch, a second switch, an error amplifier, a comparator, a frequency locked loop circuit, an inverter and a COT logic circuit. The COT buck converter is able to improve DC (direct-current) regulation efficiency and transient response time.

Abstract: A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.

Abstract: An electronic device is capable of determining a radio communications configuration. The electronic device includes a GPS module arranged for receiving an updated GPS coordinate. A controller is electronically coupled to the GPS module, and arranged for controlling the GPS module to receive the updated GPS coordinate and for determining the radio communications configuration based on the updated GPS coordinate received from the GPS module. A transmitter is electronically coupled to the controller and arranged for transmitting a message from the controller according to the determined radio communications configuration.