Abstract: A system for use in an electronic cryptosystem for providing a sender with electronic proof of receipt by an intended recipient of an electronic artifact is disclosed. The process is initiated by the recipient's requesting an artifact from the sender, who then obtains the recipient's transmission key and separately encrypts the requested artifact and an acknowledgment such that they are decryptable with first and second strictly private keys, respectively, known to and controlled by the sender. Next, the sender encrypts the encrypted artifact and encrypted acknowledgment together using the transmission key such that the message is decryptable only with a third strictly private key known to and controlled by the recipient, and transmits the encrypted message to the recipient. The recipient decrypts the message to recover the encrypted artifact, as well as the encrypted acknowledgment which is returned to the sender.

Abstract: Compliant electrically connection bumps for an adhesive flip chip integrated circuit device and various methods for forming the bumps include the steps of forming polymer bumps on a substrate or an integrated circuit die and coating the polymer bumps with a metallization layer. The polymer bump forming step includes the steps of coating a polymer material on a substrate, curing the polymer and the etching the bump pattern from the polymer material. The overcoating step includes electrolessly plating a ductile metal such as gold on the polymer bump.

Abstract: Multicell system and method for making a multicell system. Systems include relatively thin (less than about 50 mil) electrochemical cells layered upon one another to minimize volume and weight. Cells systems are formed with cells that are layered such that first charge sides of each cell are coupled to first charge sides of other cells, and such that second charge sides of each cell are coupled to second charge sides of other cells. Cells and/or cell systems is connected to other cells and/or cell systems to form battery systems by layering cells such that a first charge side of a cell are coupled to second charge side of another cell. In this manner the number of electrically insulating separators is reduced, thereby also reducing weight and volume of resulting systems.

Abstract: A multi-layered pattern recognition neural network (30) is disclosed that comprises an input layer (50) that is operable to be mapped onto an input space that includes a scan window (32). Two hidden layers (54) and (58) map the input space to an output layer (34). The hidden layers utilize a local receptor field architecture and store representations of objects within the scan window (32) for mapping into one of a plurality of output nodes. Further, the output layer (34) is also operable to store representations of desired distances between the center of the scan window (32) and the next adjacent object thereto and also the distance between the center of the scan window (32) and the center of the current object. A scanning system can then utilize the information regarding the distance to the next adjacent object, which is stored in an output vector (40) to incrementally jump to the center of the next adjacent character rather than scan the entire distance therebetween.

Abstract: A high force flip chip bonding method and system that precisely and forcefully engage a flip chip device with a corresponding wiring pattern on a substrate in a manner that prevents flip chip device and substrate shifting during force application. The method includes the steps of determining the centroid of the pattern formed by the interconnects on the flip chip device. The flip chip device is directed toward the substrate for contacting the corresponding wiring pattern with the interconnects and then the interconnects are compressed into the corresponding wiring pattern using a bonding force. The bonding force is directed along a neutral axis of deflection that is coincident with the centroid. Applying the bonding force along the neutral axis of deflection at the centroid minimizes lateral shifting of the flip chip device relative to the substrate to precisely bond the interconnects to the corresponding wiring pattern.

Abstract: A matrix-addressed diode flat panel display of field emission type is described, utilizing a diode (two terminal) pixel structure. The flat panel display includes a cathode assembly having a plurality of cathodes, each cathode including a layer of cathode conductive material and a layer of a low effective work-function material deposited over the cathode conductive material and an anode assembly having a plurality of anodes, each anode including a layer of anode conductive material and a layer of cathodoluminescent material deposited over the anode conductive material, the anode assembly located proximate the cathode assembly to thereby receive charged particle emissions from the cathode assembly, the cathodoluminescent material emitting light in response to the charged particle emissions.

Abstract: A multi-layered pattern recognition neural network that comprises an input layer (28) that is operable to be mapped onto an input space comprising a scan window (12). Two hidden layers (30) and (32) map the input space to an output layer (16). The hidden layers utilize a local receptor field architecture and store representations of objects within the scan window (12) for mapping into one of a plurality of output nodes. Each of the plurality of output nodes and associated representations stored in the hidden layer define an object that is centered within the scan window (12). When centered, the object and its associated representation in the hidden layer result in activation of the associated output node. The output node is only activated when the character is centered in the scan window (12). As the scan window (12) scans a string of text, the output nodes are only activated when the associated character moves within the substantial center of the scan window.

Abstract: A customizable circuit using a programmable interconnect and compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form long diagonal lines having a pitch determined by the basic wire segment length. Uniform capacitance effects are achieved by alternating the layers of the wire segments. The terminal ends of the segments are positioned in a plane such that segments may be connected by short links to form the desired interconnect. The links which join the line segments customize the otherwise undedicated interconnect. Resistive links may be used to minimize undesirable transmission line effects. The segment ends may also be connected through electrically programmable elements. Carrier tape bonds the integrated circuit chips to the programmable interconnect.

Abstract: A hybrid superconducting-semiconducting field effect transistor-like circuit element comprised of a superconducting field effect transistor and a closely associated cryogenic semiconductor inverter for providing signal gain is described. The hybrid circuit functions nearly as an ideal pass gate in cryogenic cross-bar applications.

Abstract: Apparatus for converting superconductor low level signals to semiconductor signal levels utilizing a continuous superconductor to semiconductor converter circuit biased for maximum gain and without the need for a clocked reset signal. Employing a unique biasing arrangement utilizing two capacitors and one transistor, this circuit has long term bias voltage retention and good power supply noise rejection ratio.

Abstract: A process for manufacturing a pin grid array package providing a plurality of electrical input and/or output connections using a plurality of stacked, but spaced apart, separate leadframes which are preformed and include a plurality of electrical leads having first and second ends for providing a plurality of different connections. An insulating layer is positioned between adjacent leadframes and the package is bonded together.

Abstract: A method of making sub-micron low work function field emission tips without using photolithography. The method includes physical vapor deposition of randomly located discrete nuclei to form a discontinuous etch mask. In one embodiment an etch is applied to low work function material covered by randomly located nuclei to form emission tips in the low work function material. In another embodiment an etch is applied to base material covered by randomly located nuclei to form tips in the base material which are then coated with low work function material to form emission tips. Diamond is the preferred low work function material.

Abstract: An improved method for inhibiting tin whisker growth involving the implantation in a tin coating of an ion or ions selected from the group Pb, Bi, Sb, Tl, Cu, Ag, Au, Cd, Mo, Cr, W, Ar, He, Ne and Kr.

Abstract: Direct fabrication of three-dimensional metal parts by irradiating a thin layer of a mixture of metal powder and temperature equalization and unification vehicle to melt the metal powder and form a solid metal film. The vehicle also protects the molten metal from oxidation. The metal powder can contain an elemental metal or several metals, the vehicle can be an organic resin or an amalgam, and the irradiation can be selectively applied by a YAG laser.

Abstract: Superconducting-semiconducting hybrid memories are disclosed. These superconducting-semiconducting hybrid memories utilize semiconductor circuits to store information, and either superconducting or semiconducting or combinations of superconducting and semiconducting circuits, with at least some superconducting circuitry used, to write and read information. The state of memory cells in the hybrid memories is determined by utilizing superconductor current sensing schemes to detect currents in the bit-line, thereby avoiding any bit-line charging delays and other problems associated with purely semiconductor memories. Additional features of the superconducting-semiconducting hybrid memories include wide margins, dense packing of memory cells, low power dissipation and fast access times. Interface curcuitry for converting superconducting signals to signals compatible with semiconductor circuits and for converting semiconductor signals to signals compatible with superconducting circuits is also disclosed.

Abstract: A three dimensional integrated circuit interconnect for connecting a plurality of chips in a module with a standard footprint for pin grid array or quad flat pack mounting. Each IC is mounted on a custom interconnect slice and tested. The slices are stacked together with electrical connections from one slice layer to the next. The module may use multi-layer ceramic slices or printed circuit board materials.

Abstract: A method of forming an etch mask and patterning a substrate. The method includes directing a particle beam at a substrate without using a mask to deposit an etch mask on the substrate which selectively exposes predetermined portions of the substrate, the etch mask consisting of particles mechanically placed on the substrate by the particle beam, and then etching the exposed portions of the substrate through the etch mask to form channels therein. The process is well suited to fabricating high density copper/polyimide multi-chip modules.

Abstract: A maskless process for forming a protected metal feature in a planar insulating layer of a substrate is disclosed. A first barrier material is disposed in a recess in an insulating layer, a conductive metal is disposed on the first barrier material such that the entire metal feature is positioned within the recess below the top of the recess, a second barrier material is disposed on the metal feature such that the second barrier material occupies the entire portion of the recess above the metal feature and extends above the top surface of the insulating layer, and the second barrier material is then polished until the top of the second barrier material is in and aligned with the top of the insulating layer. As a result, the metal feature is surrounded and protected by the first and second barrier materials, and the substrate is planarized.

Abstract: An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

Abstract: A high force flip chip bonding method and system that precisely and forcefully engage a flip chip device with a corresponding wiring pattern on a substrate in a manner that prevents flip chip device and substrate shifting during force application. The method includes the steps of determining the centroid of the pattern formed by the interconnects on the flip chip device. The flip chip device is directed toward the substrate for contacting the corresponding wiring pattern with the interconnects and then the interconnects are compressed into the corresponding wiring pattern using a bonding force. The bonding force is directed along a neutral axis of deflection that is coincident with the centroid. Applying the bonding force along the neutral axis of deflection at the centroid minimizes lateral shifting of the flip chip device relative to the substrate to precisely bond the interconnects to the corresponding wiring pattern.