Abstract: A dynamic random access memory (DRAM) includes a first bit line extending along a first direction, a first buried word line extending along a second direction, and an active region overlapping part of the first bit line and part of the first buried word line. Preferably, the active region comprises a V-shape. Moreover, the DRAM also includes at least a storage node contact overlapping one end of the active region, in which the storage node contact includes an ellipse.

Abstract: A crystal oscillator with a configuration that allows for reduction of power consumption includes a crystal element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a crystal element. The crystal element includes a first terminal coupled to a control terminal of the seventh transistor and a second terminal coupled to a first terminal of the seventh transistor. The second transistor includes a control terminal coupled to an output terminal of the crystal oscillator and a first terminal of the ninth transistor.

Abstract: A digital isolator module for high level common mode transient immunity is provided, comprising a transmitter circuit (TX), a receiver circuit (RX) and an isolation barrier which is connected there in between, wherein the transmitter circuit is electrically connected to a first ground voltage level and the receiver circuit is electrically connected to a second ground voltage level. The receiver circuit further comprises a resistance set, a high speed detector and a demodulator. By employing the proposed circuit diagram of the invention, interferences occurring at the common mode are suppressed and an RX output signal is synchronized with its input signal without having propagation delay.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a material layer having a contact pad therein; forming a dielectric layer on the material layer and the contact pad; forming a doped oxide layer on the dielectric layer; forming an oxide layer on the doped oxide layer; performing a first etching process to remove part of the oxide layer, part of the doped oxide layer, and part of the dielectric layer to form a first contact hole; performing a second etching process to remove part of the doped oxide layer to form a second contact hole; and forming a conductive layer in the second contact hole to form a contact plug.

Abstract: A method of fabricating an integrated circuit includes the following steps. A first reticle is used to form a first pattern, wherein the first pattern includes a first feature and a first jog part protruding from and orthogonal to the first feature. A second reticle is used to form a second pattern, wherein the second pattern includes a second feature, and the first feature is between the second feature and the first jog part. A third reticle is used to form a third pattern, wherein the third pattern includes a third-one feature overlapping the first jog part and a third-two feature overlapping the second feature.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner, wherein the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.

Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

Abstract: The driving apparatus for driving a touch display panel includes a first voltage generating circuit configured to generate a common reference voltage, a second voltage generating circuit configured to generate a touch driving signal, and a control circuit configured to generate a switching signal. The switching signal is at the first voltage level during display periods for providing the common reference voltage to the touch display panel. The switching signal is at the second voltage level during touch periods for providing the touch driving signal to the touch display panel. A first touch display period includes a first display period a first touch period adjacent to the first display period. A second touch display period includes a second display period and a second touch period adjacent to the second display period. The first touch display period and the second touch display period are different in time length.

Abstract: A method of forming a capacitor mask includes the following steps. A bulk mandrel and a plurality of strip mandrels are formed on a mask layer. Spacers are formed on sidewalls of the bulk mandrel and the strip mandrels. The strip mandrels are removed while the bulk mandrel is reserved. A material fills in space between the spacers and on the bulk mandrel, wherein the material has a flat top surface. A patterned photoresist is formed to cover the bulk mandrel and a part of the spacers but exposing the other part of the spacers after filling the material.

Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.

Abstract: An interconnect layout structure, having a plurality of air gaps, includes a substrate having an insulating material disposed thereon and a conductive line disposed in the insulating material and extending along a first direction. The air gaps are formed in the insulating material and are arranged end-to-end along the first direction and immediately adjacent to a same side of the conductive line. A patterned hard mask is disposed on the conductive line and has a sidewall extending along a second direction that is perpendicular to the first direction and passing between the adjacent air gaps from the top view. A via structure is formed on the conductive line and is electrically connected to the conductive line.

Abstract: A touch display panel and a manufacturing method thereof are provided. The touch display panel includes a substrate, a conductor, a first pressure sensing electrode and a second pressure sensing electrode. The conductor is stacked under the substrate, and the conductor is not connected to a bias. The first pressure sensing electrode is disposed on the substrate and disposed above the conductor. A compression zone exists between the first pressure sensing electrode and the conductor, so as to form a first pressure sensing capacitor. The second pressure sensing electrode is disposed on the substrate and disposed above the conductor. The compression zone exists between the second pressure sensing electrode and the conductor, so as to form a second pressure sensing capacitor connected in series with the first pressure sensing capacitor.

Abstract: A method for automatic inline detection and wafer disposition includes the following steps. An exposure process is performed to wafers in an exposure apparatus. A virtual inspection is performed based on log files of the exposure process. A wafer automatic disposition is performed according to a result of the virtual inspection. An automatic inline detection and wafer disposition system includes a first computer system coupled to an exposure apparatus and a second computer system coupled to the first computer system. The exposure apparatus is configured to perform an exposure process to wafers, and the first computer system is configured to perform a virtual inspection based on log files of the exposure process. The second computer system is configured to receive a result of the virtual inspection and perform a wafer automatic disposition according to the result of the virtual inspection.

Abstract: An embodiment of the invention provides an optical device including a first substrate, a light source, a second substrate, an image capturing device, a lens module and a lens holder. The light source outputs a first light beam. The second substrate includes a first surface and a second surface opposite to the first surface and closer to the first substrate. A scattered light beam which is generated by the first light beam entering an object touching the first surface of the second substrate and scattered in the object is a second light beam. The image capturing device receives a third light beam. The third light beam is the second light beam normally incident to the second surface and transmitted to the image capturing device. The lens module focuses the third light beam to be captured by the image capturing device.

Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.

Abstract: An optical device including a first substrate, a light source, a second substrate, an image capturing device, a lens module and a lens holder is provided. The light source outputs a first light beam. The second substrate includes a first surface and a second surface opposite to the first surface and closer to the first substrate. A scattered light beam which is generated by the first light beam entering an object touching the first surface of the second substrate and scattered in the object is a second light beam. The image capturing device receives a third light beam. The third light beam is the second light beam normally incident to the second surface and transmitted to the image capturing device. The lens module focuses the third light beam to be captured by the image capturing device. The lens holder is located between the light source and the image capturing device.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.

Abstract: A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.