Abstract: A nanowire transistor structure includes a substrate. A first nanowire is suspended on the substrate. A first gate line crosses and surrounds the first nanowire. The first gate line includes a first end and a second end. A second gate line crosses and surrounds the first nanowire. The second gate line includes a third end and a fourth end. An interlayer dielectric encapsulates the first end, the second end, the third end and the fourth end. A first distance between the first end and the first nanowire is smaller than a third distance between the third end and the first nanowire.

Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.

Abstract: A semiconductor device including a substrate having a fin structure surrounded by a trench isolation region; a trench disposed in the fin structure; a silicon nitride trench-fill layer disposed in the trench; an interlayer dielectric layer disposed on the silicon nitride trench-fill layer; a working gate striding over the fin structure, on the first side of the trench; a dummy gate striding over the fin structure, on the second side of the trench; a doped source region in the fin structure; and a doped drain region in the fin structure. The dummy gate is disposed between the trench and the doped drain region.

Abstract: A sub-pixel rendering data conversion apparatus including an inverse sub-pixel rendering circuit and a sub-pixel rendering circuit is provided. The inverse sub-pixel rendering circuit receives the first sub-pixel rendering data converted from the first true image data and converting the first sub-pixel rendering data to the second true image data, and the first sub-pixel rendering data includes data of the first sub-pixel rendering arrangement. The sub-pixel rendering circuit converts the second true image data to the second sub-pixel rendering data and outputs the second sub-pixel rendering data to a display panel, the second sub-pixel rendering data includes data of the second sub-pixel rendering arrangement, and the display panel includes a plurality of sub-pixels arranged in the manner of the second sub-pixel rendering arrangement.

Abstract: A display panel includes a plurality of data lines, a plurality of scan lines, a plurality of subpixels and a plurality of first demultiplexers. Each of the plurality of subpixels is coupled to at least two of the plurality of data lines and at least two of the plurality of scan lines. Each of the plurality of first demultiplexers is coupled to at least two of the plurality of scan lines.

Abstract: A method for forming a semiconductor structure is disclosed. A substrate is provided. A pad metal and a fuse metal are formed on the substrate. A liner is formed on the pad metal and on the fuse metal. An etching stop layer is formed on the portion of the liner on the fuse metal. A dielectric layer and a passivation layer are formed on the liner and on the etching stop layer. After defining a pad opening and a fuse opening in the passivation layer, a first etching step is performed to remove the dielectric layer from the pad opening and the fuse opening until the pad metal and the etching stop layer are exposed. Afterward, a second etching step is performed to remove the exposed etching stop layer from the fuse opening until the liner on the fuse metal is exposed.

Abstract: A method of rounding corners of a fin includes providing a substrate with a fin protruding from the substrate, wherein a pad oxide and a pad nitride entirely cover a top surface of the fin. Later, part of the pad oxide is removed laterally to expose part of the top surface of the fin. A silicon oxide layer is formed to contact two sidewalls of the fin and the exposed top surface, wherein two sidewalls and the top surface define two corners of the fin. After forming the silicon oxide layer, an annealing process is performed to round two corners of the fin. Finally, after the annealing process, an STI filling material is formed to cover the pad nitride, the pad oxide and the fin.

Abstract: A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.

Abstract: A magnetic memory cell includes a substrate having a memory region, a transistor within the memory region, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a cylindrical memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the memory region and the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The cylindrical memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane is lower than the first horizontal plane.

Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.

Abstract: The invention provides a display panel driving circuit and a method for capturing error information thereof. The display panel driving circuit includes a driving circuit, a pixel circuit and a timing controller circuit. The method includes: obtaining LED error information indicating errors caused by an LED of the pixel circuit; driving the LED by the drive circuit to obtain LED and driving circuit error information; obtaining driving circuit error information according to the two error information. The timing controller circuit records the error information and compensates LED attenuation by using the error information.

Abstract: A sub-pixel rendering data conversion apparatus including an inverse sub-pixel rendering circuit and a sub-pixel rendering circuit is provided. The inverse sub-pixel rendering circuit receives the first sub-pixel rendering data converted from the first true image data and converting the first sub-pixel rendering data to the second true image data, and the first sub-pixel rendering data includes data of the first sub-pixel rendering arrangement. The sub-pixel rendering circuit converts the second true image data to the second sub-pixel rendering data and outputs the second sub-pixel rendering data to a display panel, the second sub-pixel rendering data includes data of the second sub-pixel rendering arrangement, and the display panel includes a plurality of sub-pixels arranged in the manner of the second sub-pixel rendering arrangement.

Abstract: An operational amplifier applicable to a display device is provided. The operational amplifier having multiple output stages. The operational amplifier includes an input stage, an output stage selection module and a plurality of output stages. The output stage selection module is coupled to the input stage. Each of the output stages is coupled to the output stage selection module and is coupleable to drive a corresponding one of a plurality of loads. The output stage selection module is configured to selectively couple or discouple each of the output stages respectively to the input stage according to a plurality of selection signal. Furthermore, a load driving apparatus and a grayscale voltage generating circuit are also provided.

Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.

Abstract: A manufacturing method of a semiconductor device includes the following steps. Trenches are formed on a substrate, and the trenches are formed on a first region and a second region defined on the substrate. A barrier layer is formed conformally in the trenches. A first pull-down process is performed to the barrier layer on the second region. The barrier layer on the first region is covered by a first mask during the first pull-down process. A second pull-down process is performed to the barrier layer on the first region. The barrier layer on the second region is covered by a second mask during the second pull-down process. A proportion of an area of the trenches on the first region to an area of the first region is different from a proportion of an area of the trenches on the second region to an area of the second region.

Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: The disclosure proposes a playback method including displaying a first playback session which comprises an on-demand streaming session in a foreground of a display of the electronic device; switching, at a first playback time (t1), the first playback session from being displayed in the foreground to a background in which the on-demand streaming session ceases streaming; recording the t1 and a first clock time (T1) in response to switching the first playback session from being displayed in the foreground to the background; switching the first playback session back from the background to being displayed in the foreground; recording a second clock time (T2) in response to switching the first playback session back from the background to being displayed in the foreground; and changing the on-demand streaming session as being displayed in the foreground to a second playback time (t2) which is determined according to t2=t1+(T2?T1).

Abstract: A manufacturing process for a micro-device panel including the following steps is provided. A plurality of micro-device sets are formed on a transferring substrate, and each of the plurality of micro-device sets has at least one micro-device. A plurality of receiving blocks are provided. The plurality of micro-device sets are respectively transferred from the transferring substrate onto the plurality of receiving blocks to form a plurality of building blocks by a transfer head. The plurality of building blocks are placed on a receiving substrate. Finally, the adjacent building blocks on the receiving substrate are connected by a plurality of connecting devices to form the micro-device panel.

Abstract: A voltage regulator and method applied thereto are provided. The voltage regulator generates a regulated voltage in response to a reference voltage and a control code. The voltage regulator includes a voltage divider circuit, an amplifier circuit, and a power MOS array. The voltage divider circuit is configured to divide the regulated voltage to generate a feedback voltage. The amplifier circuit is configured to amplify a voltage difference between the reference voltage and the feedback voltage to generate a bias voltage. The power MOS array includes multiple transistors. Each transistor has a first terminal coupled to a power rail, a second terminal coupled to the regulated voltage, and a control terminal selectively coupled to either the power rail or the bias voltage in response to the control code.