Abstract: A system and method for reducing the time required to access peripheral devices or to perform peripheral device operations in a multiple bus architecture or hierarchical bus structure environment. A memory device is used to remember which addresses generated responses on which busses. The memory device is accessed in subsequent operations to eliminate the procedure for determining which bus is attached to the desired peripheral.

Abstract: A method of displaying a status condition of a smart battery being charged by a smart battery charger. The method includes: transmitting data from the smart battery to a computer, wherein the smart battery charger is external to the computer; processing said data in accordance with a software program being executed by a central processing unit within the computer; and displaying information obtained as a result of processing said data on a display screen coupled to the computer.

Abstract: An apparatus for enclosing an input device for a semiconductor device assembly machine including a cover configured having a cavity. The cover is configured to be placed over the input device bearing on a support surface upon which the input device is placed. The input device enclosure may also include a support surface engaging for securing the input device and limiting access to the input device. The input device enclosure may be configured as a stand alone unit or it may be incorporated with other processing device components or features. The input device enclosure may also include a looking device for securing the cover to the support surface for securing the input device and limiting access to the input device.

Abstract: Circuitry is described for interfacing a software-based modem in a computer system. Memory/modem interface circuitry is integrated within a system controller coupling a main memory with a microprocessor. A dedicated region of the main memory is configured as separate transmit data and received data buffer regions. Buffer address registers included within the system controller store values pointing to address locations within the buffer regions of the memory for next data in and next data out. The values programmed in these registers are incremented responsive to associated data transfers in/out of the buffer regions, and the transmit data and received data buffer regions function as FIFOs. The frequency and duration of processor utilization imposed by software-based modems is significantly reduced, due to FIFO operations functioning at main memory access speed.

Abstract: A usage monitor circuit monitors the amount of use of various components within a computer system. The circuit includes a plurality of timers and counters that are respectively coupled to the various components to be monitored such that the counters record the number of times the components are activated and the timers record the cumulative times the components are activated. The usage monitor circuit also includes a tamper protection unit that indicates whether the circuit has been tampered with.

Abstract: An application specific integrated circuit has at least one standard cell, integrated circuit connection circuitry connected to the at least one standard cell and at least one programmable circuit that is selectively connectable to the integrated circuit connection circuitry. The connection is made by metal mask changes. The programmable circuit is a general-purpose logic block.

Abstract: The present invention provides for an apparatus and method for securing a computer system. A security loop or tab is attached to a computer chassis and used to engage a cover that encloses at least a portion of a side of the computer chassis. Structure is provided in embodiments of the invention to releasably engage the cover with the security tab and to provide a means of locking the cover on the chassis to prevent unauthorized access to the computer system. Additionally, the securing apparatus is place in a location not readily visible to users of the computer system.

Abstract: A method for testing an IDE controller with random constraints, the method comprising: providing an IDE controller model having a primary and a secondary channel and a host interface; transmitting data patterns to a primary and a secondary device model; receiving the data patterns from the primary and secondary device models; arbitrating the transfer of the data patterns to and from the primary and secondary device models; and determining whether the data patterns returned from the primary and secondary device models match expected values.

Abstract: A memory fault correction system enables plural data bit errors in a single data word to be corrected in an efficient manner. The system divides each data word into a plurality of sub-words and creates a separate error correction code for each of the sub-words. Each of the error correction codes includes a plurality of check bits with check bit values based on the data bit values of the corresponding sub-word of the data word. The computer system includes a plurality of error correction modules each performing error correction on a separate sub-word of the data word. A memory controller rearranges the data bits of the data word when forming the sub-words such that consecutive data bits are arranged in separate sub-words.

Abstract: Chipset or core logic for attachment of the ROM BIOS within the system architecture. Although normally attached to the ISA bus, the ROM BIOS may be attached to an alternate bus (e.g., the memory bus) located within the system, thereby potentially eliminating the ISA bus from the computer system.

Abstract: A system for communicating information between requester and target devices in a computer having a multiple bus architecture. The system supports deferred transactions of cache line read requests over a host bus, e.g., the Pentium II or Pentium Pro (P6) bus. The system employs a host bridge to issue deferred transactions over the P6 bus without interrupting or involving the main processor. The system comprises a first device, electrically connected to the requester, which receives a request from the requester. The system further comprises a second device, electrically connected to the first device, which transmits the request with a defer enable signal over the P6 bus. The system further comprises a third device, electrically connected to the P6 bus, which communicates the request having a defer enable signal to the target.

Abstract: A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

Abstract: A fault tolerant method of downloading the contents of a server system log through either a local or remote client machine without intervention of the server operating system software. The remote machine accesses the server by use of a dial-in modem connection while the local machine accesses the server by a local serial connection. The system log may be stored in a non-volatile RAM which is powered by a remote interface if the server power is off. The downloaded information is displayed in a graphical user interface window to enable diagnosis and recovery of the server.

Abstract: One embodiment of the present invention provides a method for ensuring that attachments intended to be included with an electronic mail message are affixed to the message prior to release of the message from a sender's electronic mail program. This embodiment eliminates the need to initiate a follow-up transmission to forward the intended attachment. This saves the sender from potential embarrassment as well as eliminating unnecessary network traffic. In this embodiment, the method includes maintaining a modifiable list of keywords and phrases which, when found in an electronic mail message, indicate that the composer of the message intends to include an attachment with the message. Upon composition of a message, an attachment verifier scans the message for the keywords and phrases. In this embodiment, if a keyword or phrases is found in the message and no attachments have been specified, a user is alerted to the possibility that an attachment was overlooked.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

Abstract: A closure system useful for securing a device having a stylus. In a first embodiment, the closure system includes a housing having first and second housing members, the first housing member being configured to matingly contact the second housing member when the device is in a closed configuration. The stylus is received within a channel located in the second housing member. A latch release also located within the second member is controlled by the position of the stylus such that when the stylus is inserted within the channel, the latch release engages a latch located on the first member, thereby preventing the first and second members from separating. The latch release may also be used to block the latch such that the first and second housing members can not be mated when the stylus is removed from the channel. In another embodiment, a blocking device located within the second housing member and separate from the latch is utilized to prevent the device from being closed when the stylus is removed.

Abstract: The invention configures an asynchronous system to emulate a synchronous system. When an application initiates a synchronous transaction, the synchronous transaction is received by a synchronous interface. The synchronous interface, in turn, simulates a synchronous system while performing an asynchronous transaction. In one embodiment, the synchronous emulation ensures that the asynchronous transaction is completed within a configurable maximum time duration. If the asynchronous transaction has not been completed with within the defined maximum time duration, the synchronous emulation notifies the application that the desired data is not available. In another embodiment, the synchronous eumlation re-executes failed asynchronous transactions.

Abstract: One embodiment of the present invention provides a system for skipping a track on a disc in a disc player. Unlike current systems, this system does not rely on identifying tracks to be skipped based upon which slot a disc is located in. Instead, one embodiment of the present invention identifies discs based upon identification data read from discs in the disc player. Thus, one embodiment of the present invention provides an apparatus for playing discs that skips a track on a disc. The apparatus includes a disc player including a sequencing mechanism that generates a sequence of tracks from discs in the disc player. The disc player also includes an identification mechanism within the disc player that reads identification information from discs in the disc player and determines from the identification information if a specific disc is in the disc player.

Abstract: A method for issuing device requests by proxy in a system using distributed control through a multi-port switch. A device issues a request to a central switch indicating the original requester as the source rather than itself. This passes responsibility for the control of the actual data transfer back to the original requester, and the device is no longer involved.

Abstract: A PC-based home security system for monitoring the environment surrounding a PC in order to detect suspicious or uncharacteristic events. The PC-based home security system first monitors the environment, listening and watching for a threshold event. When a threshold event is detected, the PC-based home security system then conducts close surveillance of the environment in order to detect and characterize additional events. When the accumulated detected events exceed some threshold value, the PC-based home security system determines that a suspicious or uncharacteristic set of events has occurred, diagnoses those events, and takes a remedial action appropriate to the diagnosed set of suspicious circumstances.