Abstract: A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.

Abstract: A mount for a computer component such as a disk drive includes horizontal platforms having upstanding studs and a strap. The strap is movable between an open position in which a drive may be removed from or installed into the mount and a closed position in which the upstanding studs are inserted into bores in the component and the strap keeps the component in place such that the studs remain in the bore and the drive is secure. Each end of the strap travels in a vertical channel formed along a corresponding vertical wall of the mount. Each end of the strap is provided with a detent and each vertical channel includes a detent receptacle sized to engage the detent. The detent receptacle corresponds to a closed position. A second detent receptacle may also be provided to hold the strap in an open position. The detent reliably secures the drive in the closed position while allowing the strap to be moved easily between the open and closed positions.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap viuual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

Abstract: A computer and a cooling unit for cooling a computer having a housing with a first panel including an aperture, a central processing unit coupled to a circuit board, a heat exchanger coupled to the central processing unit, and a power supply positioned apart from the heat exchanger. The heat exchanger is positioned internally in the housing, and it is obstructed from the aperture in the first panel. In one particular embodiment, the cooling unit has a separate support element segregated from the power supply and an airflow director attached to the support element. The support element, for example, may have a first section attached to either the housing the motherboard, or another component of the computer apart from the central processing unit. The support element may also have a second section extending from the first section to an airflow site proximate to the heat exchanger.

Abstract: A memory controller which has multiple stages of pipelining. A request buffer is used to hold the memory request from the processor and peripheral devices. The request buffer comprises a set of rotational registers that holds the address, the type of transfer and the count for each request. The pipeline includes a decode stage, a memory address stage, and a data transfer stage. Each stage of the pipeline has a pointer to the request buffer. As each stage completes its processing, a state machine updates the pointer for each of the stages to reference a new memory request which needs to be processed.

Abstract: A system for monitoring the status of a first server in a server network with a second server in the network, and also for providing synchronization and messaging capability between the two servers, the system including: a device coupled to first and second servers for receiving commands from the first and second server; a pulse transmitter module, coupled to the first server, for transmitting a software-generated pulse waveform to said device; and a pulse receiver module, coupled to the second server, for receiving the software-generated pulse waveform, wherein the software-generated pulse includes: a first command transmitted from the first server to said device which corresponds to a logic level low of said pulse waveform, wherein the first command sets the status condition of said device to a first state; and a second command transmitted from the first server to said device which corresponds to a logic level high of said pulse waveform, wherein the second command sets the status condition of said device t

Abstract: A fault tolerant system by which individual components of a server are monitored and controlled through independent, programmable microcontrollers interconnected through a microcontroller network. An external agent can control and monitor the microcontrollers by extending the interconnection network beyond the physical server. The extension to the interconnection network converts protocols between media, and directs the microcontrollers and the state managed by the microcontrollers. Intervention of the server operating system software is not required and is not utilized for the access and control operations. A remote interface board provides the interface between the microcontroller network and an external modem that communicates with a remote client computer. The remote interface board also provides for connection to a local client computer.

Abstract: A method and apparatus for expanding the circuitry of a circuit board, such as a computer motherboard. The apparatus can include a riser card removably coupled to the circuit board and having a plurality of expansion slots for receiving expansion devices. The riser card can include a connector for receiving a second riser card having further expansion slots for removably receiving additional expansion devices. Accordingly, a single riser card can be connected to a circuit board that is installed in a chassis that can accept no more than one riser card, and a pair of such riser cards can be stacked, one upon the other, on a circuit board that is installed in a chassis that can accommodate stacked riser cards.

Abstract: A system for automatically configuring a computer system, after a device has been hot added to the computer system, which includes the following elements: a detection module which automatically detects a hot added device; a first configuration module which automatically configures the device; an identification module which automatically identifies a device type for the device; a location module which automatically determines the location where the device has been hot added; a driver module which automatically loads a driver corresponding to the hot added device; and a second configuration module which automatically modifies a configuration file so as to integrate the hot added device into the system.

Abstract: A laser marking station housing a laser marking head within a walled, substantially bottomless enclosure defining an opening into which a tray carrier bearing a tray of IC packages to be marked may be raised to place the tray at correct laser focal length and effect complete (laser) light containment within the enclosure using the tray carrier to effect closure of the opening. A lift mechanism for raising the tray carrier into the enclosure is also disclosed.

Abstract: A computer apparatus for monitoring and integrating changes made to a computer system having a plurality of operating systems installed thereon is provided. The apparatus monitors and records changes in accordance with user preferences for a first operating system. When the computer is booted for use with a second operating system, the apparatus integrates into the second operating system and associated programs the changes made during operation of the computer with the first operating system.

Abstract: A keyboard assembly for a personal computer. In one embodiment, the keyboard assembly has a housing and an actuator coupled to the housing. The housing may have an elongated front edge, an elongated rear edge, a lower surface, and an upper surface. A plurality of keys may project from the upper surface of the housing. The actuator is coupled to the housing to rotate the housing about a rotational axis for changing the inclination of the housing and the keys during operation. For example, the actuator may continuously rotate the housing about a rotational axis during operation in a manner that causes a computer operator to continuously flex his/her wrists. In another embodiment, the housing may be attached to a separate base that has a bottom surface for resting on a support surface. The base may also have a top surface with a channel extending along the rotational axis that is defined by a curved surface with a circular cross-section.

Abstract: Substrate handling apparatuses for selectively moving a microelectronic-device substrate assembly in a processing machine having a first side, a second side opposite the first side, and a processing path extending from the first side to the second side. The processing machine can also include a cassette proximate to a second side of the processing station that moves to position a substrate at the processing path. In one aspect of the invention, the substrate handling apparatus includes a guide member attached to the processing machine, an arm slidably attached to the guide member, and a clamp attached to the arm. The guide member is generally fixedly attached to the processing machine, and the guide member generally has a shape corresponding to the processing path.

Abstract: A fault-tolerant computer system includes a processor and a memory, connected to a system bus. The system includes at least two mirrored circuits, at least two mirrored IO devices, a detection means and a re-route means. The two mirrored circuits each include an interface to the system bus, and an IO interface. The input/output interface of each of the mirrored circuits is connected to one of the two mirrored IO devices. Detection means detect a load imbalance in the data transfer between the system bus and either one of the two mirrored IO devices. In response to the detection of a load imbalance, the re-route means re-routes the data transfer between the system bus and the other one of the two mirrored IO devices. In another embodiment, a fault-tolerant computer system includes a first, second and third IO bus, legacy devices, and two IO devices. The first IO bus is connected to the system bus. The legacy devices are connected to the first IO bus.

Abstract: One embodiment of the present invention provides a game unit controller for controlling a game unit in a manner that simulates the feel of a bicycle, scooter, motorcycle, all-terrain vehicle, snowmobile, jet ski, or the like. The game unit controller includes a base with a clamp coupled thereto for securing the base to a peripheral edge of a table. Also included is a pivoting unit movably coupled to the base for generating control signals upon movement thereof. A handlebar assembly is coupled to the pivoting unit for being gripped by a user and moving the pivoting unit, thereby effecting the generation of the control signals which in turn control the associated game unit.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A computer system and method for filtering unauthorized electronic mail messages that are sent by senders to a user. The system includes a list of the identifications of the senders who are authorized to send an electronic mail message to the user. When an electronic mail message is received, the system determines whether the sender of the electronic mail message is authorized by determining whether the identification of sender in the electronic mail message is in the list of the identifications of the senders who are authorized. When the sender of the electronic mail message is determined to be authorized, the system stores the electronic mail message in an Inbox folder. When the sender of the electronic mail message is determined to be not authorized, the system stores the electronic mail message in a Junk Mail folder.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.

Abstract: A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.

Abstract: A cooling system for cooling components of a computer is provided. The cooling system includes a DC fan which operates at a speed which is substantially proportional to the voltage that is applied to the fan. A zener diode voltage divider is connected in series between a voltage source and a first input of the fan. The second input of the fan is connected to a reference voltage source. A switch is also connected in series between the voltage source and the first voltage input of the fan so as to be connected in parallel with the zener diode voltage divider. When the switch is in a first position, the voltage produced by the voltage source is applied directly to the fan allowing the fan to operate at a first speed. When the switch is in a second position, the voltage from the voltage source is applied to the first input of the fan through the zener diode such that the first input of the fan receives a second voltage that is less than the first voltage thereby causing the fan to operate at a second speed.