Abstract: Memory devices may perform read operations and write operations with different bit error correction rates to satisfy a bit error correction rate. However, improving the bit error correction rate of the memory device using a single type of read command and/or write commands may result in longer read and write commands. Moreover, using longer read and write commands may result in undesirable higher memory power consumption and may reduce memory throughput. Accordingly, memory operations are described that may use combination of commands with increased bit error correction capability and reduced bit error correction capability. For example, the read operations may use multiple (e.g., at least two) sets or groupings of read commands and the write operations may use multiple (e.g., at least two) sets or groupings of write commands.

Abstract: Methods, systems, and devices for reduced-voltage operation of a memory device are described. A memory device may operate in different operational modes based on a value of a supply voltage fir the memory device. For example, when the value of the supply voltage exceeds both a first threshold voltage and a second threshold voltage, the memory device may be operated in a normal operation mode. When the value of the supply voltage is between the first threshold voltage and the second threshold voltage, the memory device may be operated in a low voltage operation mode, which may be a reduced performance mode relative to the normal operation mode. When the value of the supply voltage is below the second threshold voltage, the memory device may be deactivated.

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

Abstract: Methods, systems, and devices for cleaning memory blocks using multiple types of write operations are described. A counter may be incremented each time a write command is received. In response to the counter reaching a threshold, the counter may be reset and a flag may be set. Each time a cleaning of a memory block is to take place, the flag may be checked. If the flag is set, the memory block may be cleaned using a second type of cleaning operation, such as one using a force write approach. Otherwise, the memory block may be cleaned using a first type of cleaning operation, such as one using a normal write approach. Once set, the flag may be reset after one or more memory blocks are cleaned using the second type of cleaning operation.

Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

Abstract: Disclosed herein is an apparatus that includes a semiconductor substrate having a main surface extending in a first direction and a second direction different from the first direction and a conductive pattern formed over the main surface of the semiconductor substrate. The conductive pattern includes a first section extending in the first direction, a second section extending in the second direction, and a third section connected between the first and second sections. The third section of the conductive pattern has a first slit extending in a third direction different from the first and second directions.

Abstract: Methods and apparatuses are provided for aligning read data in a stacked semiconductor device. An example apparatus includes a stacked semiconductor device comprising stacked first and second die. The stacked semiconductor device includes a first path having a first align (first die) and second align (second die) circuits for providing read data from the second die and a second path having a first replica align (first die) and second replica align (second die) circuits. During a timing align operation, a first control circuit sets the first align and replica align circuits to a first delay value based on a propagation delay of a clock signal through the second replica align circuit. After setting of the first delay value, a second control circuit sets the second align and replica align circuits to a second delay value based on a difference in propagation delays through the first and second replica align circuits.

Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.

Abstract: Methods, systems, devices, and computer-readable media for performing read disturb management of a memory device. A method includes retrieving a value of a read counter for a block associated with a read request issued to a memory array; refreshing valid word lines in the block if the value of the read counter exceeds a first threshold; identifying a set of valid word lines in the block if the value of the read counter exceeds a second threshold, the second threshold lower than the first threshold; identifying a subset of the set of valid word lines, the subset of the set of valid word lines including word lines having an error rate above a pre-configured error rate threshold; and refreshing the subset of the set of valid word lines.

Abstract: Semiconductor device assemblies with improved ground connections, and associated systems and methods are disclosed. In one embodiment, a semiconductor device assembly may include one or more semiconductor dies mounted on an upper surface of a package substrate. Further, the package substrate includes a bond pad disposed on the upper surface, which may be designated as a ground node for the semiconductor device assembly. The bond pad may be electrically connected to an electromagnetic interference (EMI) shield of the semiconductor device assembly through a conductive component attached to the bond pad and configured to be in contact with the EMI shield at a sidewall surface or a top surface of the semiconductor device assembly, thereby forming the ground connection. Such ground connection may reduce a processing time to form the EMI shield while improving yield and reliability performance of the semiconductor device assemblies.

Abstract: A method includes forming a plurality of first line-shaped mask patterns over a substrate including a memory cell region and an array edge region; forming a plurality of second line-shaped mask patterns over the plurality of first line-shaped mask patterns; removing first portions from the plurality of first line-shaped mask patterns in the memory cell region to leave a plurality of island-shaped mask patterns above the memory cell region; removing second portions from the plurality of first line-shaped mask patterns in the array edge region to leave a holes-provided mask pattern above the array edge region; forming a mask pattern which includes a plurality of holes provided on portions; and forming, with the mask pattern which includes the plurality of holes, a plurality of contact holes in the array edge region to provide a plurality of contact electrodes connected to a plurality of word-lines.

Abstract: Disclosed herein is an apparatus that includes a first power ESD protection circuit arranged in a first circuit area; a plurality of data I/O circuits arranged in a second circuit area adjacent to the first circuit area in a first direction; a plurality of data I/O terminals arranged in the second circuit area, each of the plurality of data I/O terminals being coupled to an associated one of the plurality of data I/O circuits; a plurality of first power terminals arranged in the second circuit area; and a first power line extending in the first direction, the first power line coupling the plurality of first power terminals to the first power ESD protection circuit.

Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

Abstract: Methods, systems, and devices for receive-side crosstalk cancelation are described. A device that receives multiple signals over different transmission lines may include a circuit for canceling crosstalk. The circuit may include one or more capacitors or inductors that are coupled with the inputs of multiple receive circuits. The circuit may also include a set of resistors that are coupled with the receive circuits. In some cases, the device may dynamically configure the cancelation circuit to provide a particular bandwidth or strength of cancelation. In such cases, the device may configure the circuit autonomously or based on control information from another device.

Abstract: Devices and techniques for non-blocking external device calls are described herein. Specifically, when a processor receives an instruction with a no-return indication from a thread for a device, the processor can increase a counter corresponding to the thread based on the no-return indication. The processor can then continue execution of the thread without waiting for a return value from the device. When a return value is received for the instruction, the processor can decrement the counter. While the counter is not zero, the processor prevents the thread from completing (exiting).

Abstract: A system includes a charge pump to charge wordlines of a memory array, a pump regulator coupled including a level detector, and dynamic clock logic coupled between the level detector and an oscillator. The logic provides clock signals to the charge pump and is to perform operations including causing the oscillator to output, to the charge pump during a first time period of a recovery period of the charge pump, a first clock signal having a lower frequency than output during a time period preceding the recovery period. The operations further include causing the oscillator to output, to the charge pump during a second time period of the recovery period that follows the first time period, a second clock signal having a higher frequency than output during the time period preceding the recovery period.

Abstract: Devices, methods, and media are described for runtime memory allocation to avoid defects. One embodiment includes assigning a plurality of memory blocks of a memory sub-system to a plurality of erase groups, such that each erase group of the plurality of erase groups comprises two or more memory blocks of the plurality of memory blocks. A bad block association is determined for each erase group of the plurality of erase groups. Prior to a memory condition being met, memory resources of the memory sub-system are allocated by erase group based on a first set of criteria which are based at least in part on the bad block association for each erase group in order to prioritize use of erase groups with fewer bad blocks.

Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

Abstract: An example method of cursor seek operations using deleted record spans in memory sub-systems comprises: receiving, by a processing device, a request to search for a first data element of a key-value data store, the request specifying a first key associated with the first data element; determining that the first key is within a range of deleted data elements comprising a plurality of deleted data elements of the key-value data store; identifying a tail key associated with a tail element of the range of deleted data elements; identifying a second data element in the key-value data store, wherein the second data element is associated with a second key that follows the tail key in a specified order of keys; and providing the second data element in response to the request.