Abstract: A memory system includes a memory device comprising a content addressable memory (CAM) block comprising a plurality of key tables each storing a respective plurality of stored search keys. The memory system further includes a processing device that receives, from a requestor, an input search key and an indication of one of the plurality of key tables and identifies a match between the input search key and one of the plurality of stored search keys in the one of the plurality of key tables. The one of the plurality of stored search keys has an associated offset value indicating a location in a sorted string table (SSTable) corresponding to the one of the plurality of key tables. The processing device further reads the offset value from the one of the plurality of key tables and returns, to the requestor, the offset value read from the one of the plurality of key tables. The requestor can retrieve, from the location in the SSTable, data representing a value associated with the input search key.

Abstract: A target value of programmed bits of a first programming distribution of a set of programming distributions associated with a memory device is established. A first read voltage level is applied to a wordline portion of the memory device. A count of programmed bits in the set of programming distributions corresponding to the first read voltage level is determined. A measured ratio of the programmed bits of the first programming distribution to the count of programmed bits in the set of programming distributions is determined. The target value is compared to the measured ratio to determine a comparison result. An action is executed in view of the comparison result.

Abstract: Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes an electronic circuit, a first set of SCRC switches, and a second set of SCRC switches. The electronic circuit includes first circuitry and second circuitry. The first set of SCRC switches are at one or more SCRC regions of an integrated circuit device including the electronic circuit. The first set of SCRC switches are configured to provide power to the first circuitry. At least one second SCRC switch of the second set of SCRC switches is positioned between one of the first set of SCRC switches and another of the first set of SCRC switches. The second set of SCRC switches is configured to provide power to the second circuitry.

Abstract: A device stand for a portable device, comprising a foldable extension leg which supports the portable device at a cable connection instead of directly supporting the portable device itself. In one or more embodiments, the device stand can be connected to a storage device such as a flash drive, or can directly incorporate a storage device into its form.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may directly access a portion of memory array that is otherwise reserved for ECC functionality of a memory device. The memory array may correspond to a set of memory addresses, where each memory address of the set corresponds to a first portion of the memory array (e.g., user data plane) and to a second portion of the memory array (e.g., ECC plane). The second portion may be configured to store ECC data or second user data or metadata based on whether the ECC functionality is enabled or disabled. The memory device may determine a command directed to the memory address of the set is configured to access the first portion or the second portion based on a status of a pin associated with the command.

Abstract: Systems, apparatuses, and methods for predictive memory access are described. Memory control circuitry instructs a memory array to read a data block from or write the data block to a location targeted by a memory access request, determines memory access information including a data value correlation parameter determined based on data bits used to indicate a raw data value in the data block and/or an inter-demand delay correlation parameter determined based on a demand time of the memory access request, predicts that read access to another location in the memory array will subsequently be demanded by another memory access request based on the data value correlation parameter and/or the inter-demand delay correlation parameter, and instructs the memory array to output another data block stored at the other location to a different memory level that provides faster data access speed before the other memory access request is received.

Abstract: Examples described herein utilize multi-layer neural networks, such as multi-layer recurrent neural networks, to estimate a bit error rate (BER) of encoded data based on a retrieved version of encoded data (e.g., data encoded using one or more encoding techniques) from a memory. The neural networks may have nonlinear mapping and distributed processing capabilities which may be advantageous to estimate a BER of encoded data, e.g., to facilitate decoding of the encoded data. In this manner, neural networks described herein may be used to improve or facilitate aspects of decoding at ECC decoders, e.g., by comparing an estimated BER to a threshold (e.g., a threshold BER level) prior to decoding of the encoded data. For example, an additional NN activation indication may be provided, e.g., to indicate that the encoded data may be decoded or to indicate that error present in the encoded data is to be reduced.

Abstract: A semiconductor device includes a substrate; a die attached over the substrate; and a metal enclosure continuously encircling a space and extending vertically between the substrate and the die.

Abstract: Methods, systems, and devices for differential sensing for a memory device are described. A memory device in accordance with examples as disclosed herein may include a sense component having a signal development component for generating a sense signal, a reference component for generating a reference signal, and a tail component coupled with the signal development component and the reference component. The tail component may be configured for canceling common aspects of the sense signal and the reference signal. Additionally or alternatively, a memory device in accordance with examples as disclosed herein may include a sense component having a sense amplifier configured to operate in multiple power domains, with one power domain associated with sense signal and reference signal generation and comparison, and another power domain associated with logical signal or information transfer.

Abstract: Transistors having a control gate isolated from a first region of semiconductor material having a first conductivity type, first and second source/drain regions having a second conductivity type different than the first conductivity type and formed in the first region of semiconductor material, and a second region of semiconductor material having the first conductivity type in contact with the first region of semiconductor material, wherein the first region of semiconductor material is between the control gate and the second region of semiconductor material, wherein the first region of semiconductor material has a first width, and wherein the second region of semiconductor material has a second width, less than or equal to the first width, as well as memory containing such transistors.

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, changes to local versions of the ANN can be combined with a master version of the ANN. In the system, a first device can include memory that can store the master version, a second device can include memory that can store a local version of the ANN, and there can be many devices that store local versions of the ANN. The second device (or any other device of the system hosting a local version) can include a processor that can train the local version, and a transceiver that can transmit changes to the local version generated from the training. The first device can include a transceiver that can receive the changes to a local version, and a processing device that can combine the received changes with the master version.

Abstract: Methods, systems, and devices for transition structures for three-dimensional memory arrays are described. A memory device may include a staircase region which includes a set of vias. The set of vias may include a first subset of vias which couple respective word line plates of the memory region with associated word line decoders, and a second subset of vias which are electrically isolated from the word line plates. The second subset of vias may be arranged in one or more rows positioned between the first subset of vias and the memory region. In some cases, the second subset of vias may be positioned above respective conductive contacts. Additionally or alternatively, the second subset of vias may be positioned above a common conductor shared with pillars of the memory region.

Abstract: An electronic device comprises an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials. The channel material comprises a heterogeneous semiconductive material varying in composition across a width thereof. Related electronic systems and methods are also disclosed.

Abstract: Methods, systems, and devices for unmap operation techniques are described. A memory system may include a volatile memory device and a non-volatile memory device. The memory system may receive a set of unmap commands that each include a logical block address associated with unused data. The memory system may determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system may select a first procedure for performing the set of unmap commands different from a second procedure (e.g., a default procedure) for performing the set of unmap commands and may perform the set of unmap commands using the first procedure. If the one or more parameters do not satisfy the threshold, the memory system may perform the set of unmap commands using the second procedure.

Abstract: A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.

Abstract: A system comprises a plurality of memory devices storing a set of codewords and a processing device, operatively coupled to the plurality of memory devices, to perform operations including: detecting a power-on of the system; determining a read-retry trigger rate (TR) based on reading a subset of the codewords during a time interval directly after actual initialization of the plurality of memory devices, wherein the time interval includes a time period before entering a normal operating mode, and no full-memory refresh operation is performed during the normal operating mode; determining whether the TR satisfies a threshold criterion; and in response to the TR not satisfying the threshold criterion, initializing the full-memory refresh operation of the plurality of memory devices.

Abstract: A memory access operation performed on a first memory unit of a memory device is detected. A counter associated with the first memory unit is modified. It is determined that the counter satisfies a threshold criterion, wherein the threshold criterion is based on a random or pseudo-random number within a margin of an average number of memory access operations. A refresh operation is performed on a second memory unit.

Abstract: A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.

Abstract: Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing.

Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.