Abstract: A video processing system includes input and output address generators. The address generators are capable of generating linear addresses associated with data to be read from and written to a device. The linear address is converted to a random address so that data associated with a macroblock may be read from the device and written to the device.

Abstract: A video input processor is provided to process different input video format, including RGB, RGB Bayer, YUV 4:2:2 interlaced and progressive video data. The video input processor also uses an advanced algorithm to efficiently convert video data in RGB color space to YUV color space. The video input processor further enables multi-functions such as video image scaling, video image filtering before the video data are output for further video compression.

Abstract: A system and method for efficiently performing an inverse telecine procedure includes an inverse telecine module that converts input frames of video information into corresponding output frames by applying an inverse telecine policy to the input frames. A motion statistics generator then calculates motion statistics results corresponding to the output frames. A synchronizer module then compares the motion statistics results to entries in a synchronization table for determining whether the inverse telecine procedure is correctly synchronized. The synchronizer module may then reposition a current start boundary of the inverse telecine procedure whenever the inverse telecine procedure is not correctly synchronized.