Abstract: Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defined on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

Abstract: A method for forming an emitter tip for use in a field emission device. An emitter layer is provided over a substrate. The emitter layer is overlaid with a blanket dielectric which is in turn overlaid by a masking layer. In a first etching operation, a masking island and an underlying dielectric island are formed from the masking layer and the blanket dielectric, respectively. These islands serve as a masking structure during subsequent etching processes by which an emitter tip is formed from the emitter layer. Accordingly, a second etching operation is conducted, whereby an etch chemistry which exhibits both isotropic and anisotropic characteristics is used to remove a portion of the emitter layer by undercutting beneath the masking structure. A third etching operation is conducted, wherein the etch chemistry is substantially more anisotropic than the etch chemistry of the second etching operation.

Abstract: A method and system for bypassing command pipelines in a pipelined memory command generator is used whenever commands must be generated with a latency that is shorter than the latency at which commands can be generated using the command pipelines. The timing of commands issued by the command pipelines is a function of a digital word, and the digital word therefore indicates the latency of the command generator. When the digital word corresponds to a latency that is shorter than the latency at which the command pipeline can generate commands for read and write operations, a bypass circuit—rather than the command pipeline—generates the commands. The bypass circuit is capable of generating the commands with a latency that is shorter than the latency at which the command pipeline is capable of issuing the commands. In addition to issuing the commands, the bypass circuit generates an inhibit signal to prevent the command pipelines from generating duplicate commands.

Abstract: An apparatus and method for programming the memory cells of a multistate memory. The method involves the collapsing of data before transmitting to the memory cells. A controller generates optimized program pulses of high voltage to apply to the memory cells. The pulses vary in amplitude and time, depending on the state level being transitioned. Program verify is performed by reading the programmed data back into the controller where it is compared with the original value intended for programming. This compare operation modifies the data read and initial data to reflect which memory cells require further programming. The modified data is again collapsed and sent to the memory for further programming and verify cycles until a monitoring circuit within the controller detects that no further programming is required.

Abstract: Polishing chucks, semiconductor wafer polishing chucks, abrading methods, polishing methods, semiconductor wafer polishing methods, and methods of forming polishing chucks are described. In one embodiment, a polishing chuck includes a body dimensioned to hold a work piece, and a multi-positionable, force-bearing engagement surface is positioned on the body to engage at least a portion of a work piece held thereby. The surface has an undeflected position, and is bi-directionally deflectable away from the undeflected position. In another embodiment, a yieldable engagement surface is provided on the body and has a central area and a peripheral area outward of the central area. One of the central and peripheral areas is movable, relative to the other of the areas to provide both inwardly and outwardly flexed surface configurations. In yet another embodiment, a generally planar surface is provided on the body and positioned to receive the work piece thereagainst.

Abstract: A multiple die package may include a pair of dies having bonding pads and a front surface on which the bonding pads are located. The front surface is facing the same direction. At least one of the dies is secured to a lead frame. A spacer spaces the die from one another. At least one of the dies is spaced from the leadframe by a distance greater than the thickness of the die.

Abstract: An oxidation diffusion barrier stack includes an inorganic antireflective material layer formed on a semiconductor substrate assembly and an oxidation diffusion barrier layer formed on the inorganic antireflective material layer. Further, another oxidation diffusion barrier stack may include a pad oxide layer formed on a semiconductor substrate, an oxidation diffusion barrier layer, and an inorganic antireflective material layered between the pad oxide and the oxidation diffusion barrier layer. Yet further another oxidation diffusion barrier stack may include a first oxidation diffusion barrier layer, a second oxidation diffusion barrier layer, and an inorganic antireflective material layered between the first and second oxidation diffusion barrier layers.

Abstract: The invention provides a unique method and apparatus for detecting defects in an electronic device. In one preferred embodiment, the electronic device is a semiconductor integrated circuit (IC), particularly one of a plurality of IC dies fabricated on a wafer of silicon or other semiconductor material. The defect detection operation is effectuated by a unique combination of critical dimension measurement and pattern defect inspection techniques. During the initial scan of the surface of the wafer, in an attempt to locate the appropriate area for a critical dimension (CD) feature or element that is to be measured, a “best fit” comparison is made between a reference image and scanned images. The critical dimension measurements are conducted on a “best fit” image. In addition, a “worst fit” comparison is made between the reference and scanned images. A “worst fit” determination represents pattern distortions or defects in the ICs under evaluation.

Abstract: A system and method of efficiently transferring a cache line of data between a cache memory to a processor. A first group of M words is transferred between the cache memory and the processor in a first cache transfer cycle, where the first group of M words includes a tag word and M-1 words from the plurality of data words in the cache line. A second group of M words is transferred between the cache memory and the processor in a second cache transfer cycle, where the second group of M words includes M additional words from the plurality of data words. The process continues until the entire cache line has been transferred between the cache memory and the processor.

Abstract: According to one embodiment of the invention, a high pressure anneal is utilized to form titanium silicide at the bottom of a contact hole, at a pressure of at least approximately 1.1 atmospheres, from a reaction between deposited titanium and underlying silicon. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized. According to another embodiment of the invention, a conductive plug fill material is deposited within a contact hole such that the plug structure is relatively free of voids. Either during deposition of the conductive plug fill material or after such deposition, the conductive plug fill material is subjected to a high pressure force-fill, at a pressure of at least approximately 1.1 atmospheres. When such high pressures are used, temperatures of less than approximately 700 degrees Celsius are utilized for the force-fill. Aluminum can be used for the conductive plug fill material when using this embodiment of the invention.

Abstract: Shallow trench isolation regions in a semiconductor device are formed by utilizing sacrificial spacers such as polysilicon spacers having a rounded shape to form trench isolation areas. The spacer shape is transferred into a semiconductor substrate during an etching process to define the profile of the trench, resulting in a trench with substantially rounded upper and lower corners in the substrate. An oxide filler material is deposited in the trench and over the substrate to form a covering layer. The covering layer is then polished back to form a filled trench region which electrically isolates active areas in the substrate. The polishing step can be performed by a blanket dry etching procedure, or by a combination of chemical/mechanical planarization and wet etching. The rounded shape of the trench improves the electrical characteristics of the trench such that current leakage is decreased, and also provides a more optimized trench profile for filling the trench with the filler material.

Abstract: Semiconductor capacitor constructions, DRAM cell constructions, methods of forming semiconductor capacitor constructions, methods of forming DRAM cell constructions, and integrated circuits incorporating capacitor structures and DRAM cell structures are encompassed by the invention. The invention includes a method comprising: a) forming an opening within an insulative layer and over a node location; b) forming a spacer within the opening to narrow the opening, the spacer having inner and outer surfaces, the inner surface forming a periphery of the narrowed opening; c) removing a portion of the insulative layer from proximate the outer surface to expose at least a portion of the outer surface; d) forming a storage node layer in electrical connection with the node location, extending along the spacer inner surface, and extending along the exposed spacer outer surface; and e) forming a dielectric layer and a cell plate layer operatively proximate the storage node layer.

Abstract: An improved photolithography technique is provided whereby the beneficial effects of using an anti-reflective coating may be realized while maintaining critical dimensions in each subsequent step. This improvement is realized by the treatment of the anti-reflective coating with a gaseous plasma or a solution of sulfuric acid and hydrogen peroxide. By treating the anti-reflective coating with gaseous plasma or solution of sulfuric acid and hydrogen peroxide, no “footing” results and the critical dimensions as set by the photoresist mask are preserved to provide an accurately patterned mask for subsequent steps.

Abstract: An interconnect apparatus for testing bare semiconductor dice comprises raised contact members on a semiconductive substrate. The contact members are covered with an insulation layer and a conductive cap connected by a conductive trace to a testing circuit. The trace is covered with coaxial layers of a silicon containing insulation and a metal for shielding the trace from “cross-talk” and other interference. An apparatus for simultaneous testing of multiple dies on a wafer has thermal expansion characteristics matching those of the semiconductor die or wafer and provides clean signals.

Abstract: A contact is selectively formed in a contact hole in an insulating layer deposited on a silicon substrate. The contact hole exposes a portion of the substrate. The contact is formed by selectively forming a first layer of titanium silicide in the contact hole on the exposed portion of the substrate. A layer of titanium nitride is then selectively formed on the first layer of titanium silicide. A second layer of titanium silicide is thereafter selectively formed on the layer of titanium nitride to form the contact.

Abstract: A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a second average deposition rate less than the first average deposition rate over the wordline constructions. A reduced gap having a second aspect ratio less than or equal to a first aspect ratio of the original gap may be provided. An integrated circuit includes a pair of wordline constructions separated by a gap therebetween in areas where the wordline constructions do not cover an underlying semiconductive substrate. A layer of substantially boron free silicon oxide material has a first thickness over the substrate within the gap and has a second thickness less than the first thickness over the wordline constructions.

Abstract: A method for forming a capacitor includes forming a substrate having a node location to which electrical connection to a capacitor is to be made; forming an inner capacitor plate over the node location, the inner capacitor plate having an exposed sidewall; forming an oxidation barrier layer over the exposed inner capacitor plate sidewall; forming a capacitor dielectric plate over the inner capacitor plate, the oxidation barrier layer restricting oxidation of the inner capacitor plate sidewall during formation of the capacitor dielectric plate; and forming an outer capacitor plate over the capacitor dielectric plate. A capacitor is further described which includes an inner capacitor plate having at least one sidewall; an oxidation barrier layer positioned in covering relation relative to the at least one sidewall; a capacitor dielectric plate positioned over the inner capacitor plate; and an outer capacitor plate positioned over the capacitor dielectric plate.

Abstract: A method of forming emitter tips for use in a field emission array is disclosed. The tips are formed by utilizing a polymer residue that forms during the dry etch sharpening step to hold the mask caps in place on the emitter tips. The residue polymer continues to support the mask caps as the tips are over-etched, enabling the tips to be etched past sharp without losing their shape and sharpness. The dry etch utilizes an etchant comprised of fluorine and chlorine gases. The mask caps and residue polymer are easily removed after etching by washing the wafers in a wash of deionized water, or Buffered Oxide Etch.

Abstract: The present invention relates to a chip package and to methods of testing a chip package wherein contact to chip leads is made by a configuration of testing probes in such a manner so as to allow for shorter, tighter-pitch, and more robust chip leads that will not short out into neighboring adjacent chip leads. The present invention also relates to a chip package wherein the terminal ends of the chip leads are constrained in a dielectric medium such that package testing may be carried out before final sizing of chip lead lengths.

Abstract: Laser-assisted chemical vapor deposition is used to form spacers at desired locations in a field emission display. The spacers can be designed with different shapes to provide increased strength and also to be formed differently depending on the their location on the display.