Abstract: A circuit for a sense amplifier (14) for use with a memory device (10). The circuit includes two devices (40 and 42) that are controlled by a selector (44). The first device (40) drives the sense amplifier (14) with a first current level. The second device (42) drives the sense amplifier (14) with a second current level, different from the first current level. The selector (44) is coupled to the first and second devices (40 and 42) so as to selectively couple one of the first and second devices (40 and 42) to the sense amplifier (14) based on a power supply voltage of the memory device (10).

Abstract: A method of monitoring a process of manufacturing a semiconductor wafer including an area of hemispherical grain polysilicon, the method comprising providing a probe including a liquid conductor; and performing a capacitance-voltage measurement with the probe, using a quasi-static measurement method, to determine capacitance-voltage characteristics at the area of hemispherical grain polysilicon.

Abstract: A liquid dispense apparatus including a chuck having a support surface, a dispense nozzle directed toward the support surface, and a controller. The controller is connected to the dispense nozzle and the chuck and contains instructions which, when executed by the controller, perform the method including rotating the chuck at a first speed, dispensing a process liquid from the dispense nozzle, rotating the chuck at a reduced second speed, and distributing the process liquid while rotating the chuck at the reduced second speed.

Abstract: A method of disposing a wafer on a support member protruding from a surface. The method includes supporting the wafer in a first position defined by a lift extending through the surface and manipulating the surface to place the wafer on the support member.

Abstract: A memory device which includes intermediate storage, or cache, and unidirectional data paths coupling the intermediate storage to external input/output. The invention improves the response of the memory device by eliminating dual latencies associated with the transition from a write request to a read request. The method of use of the invention and systems incorporating the invention are further described.

Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: The invention encompasses batteries, battery electrodes and methods of forming batteries and battery electrodes. In one aspect, the invention includes a method of forming a battery electrode comprising: a) forming an electrode material mixture, the electrode material mixture comprising electrode active material, a conductive medium, and EPM; and b) curing the electrode material mixture to form an electrode having a thickness of less than 24 mils. In another aspect, the invention includes a battery comprising: a) a first electrode comprising: i) a thickness of less than 24 mils; ii) electrode active material; iii) a conductive medium; and iv) a binder comprising EPM; b) a second electrode; and c) an electrolyte between the first and second electrodes. In yet another aspect, the invention encompasses a battery electrode comprising EPM and a thickness of greater than 0 and less than 24 mils.

Abstract: The present invention is a method and apparatus for a very low profile ball grid array package. A substrate is provided with an aperture. A thin sheet material is secured to the substrate, covering the aperture, so as to form a cavity. A semiconductor die is mounted in the formed cavity on the thin sheet material. The semiconductor die is encapsulated with the thin sheet material supporting it during encapsulation. The use of the thin sheet material to form the cavity is a cost effective way to construct a ball grid array package having a very low profile.

Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.

Abstract: A synchronous semiconductor memory device has improved layout and circuitry so as to provide rapid operation. Data paths between sub-arrays and memory cells and corresponding DQ pads are equalized to provide approximately equal line delays, transmission losses, etc. Input clock circuitry converts a “asynchronous” external clock signal and external clock enable signal to an internal “synchronous” clock signal. Input command signals are not stored in input registers, but instead are latched so as to provide such input signals rapidly downstream. Multiple redundant compare circuitry is provided to improve delays inherent in selecting between external or internal addresses. Input/output pull up circuitry is enabled during both read and write operations, but shortened during write operations. Two or more voltage pump circuits are employed that permit sharing of power therebetween to compensate for increased power demands to row lines, data output lines, etc.

Abstract: A method of constructing a conductive via spacer within a dielectric layer located between a first metal layer and a second metal layer includes the steps of depositing a conductive spacer layer within the opening and over the first metal layer. A portion of the conductive spacer layer is removed to leave a conductive spacer within the opening. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers. The spacer preferably comprises a material selected from the group comprising refractory metal silicides and nitrides. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.

Abstract: A memory device and method in which the capacitor lower electrode within the memory cell array and a first interconnection layer within the peripheral circuitry are provided simultaneously from the same conductive material. The capacitor upper electrode and a second interconnection layer within the peripheral circuitry are also provided simultaneously from the same conductive material.

Abstract: A system is described for providing pulses to test a semiconductor device, such as a memory device. The system includes several voltage sources, each voltage source being coupled to an output terminal through a pass gate. A control logic circuit provides a control signal to each of the pass gates to render the pass gates conductive in a sequence. A voltage generated by each voltage source is coupled to the output terminal in a sequence to generate a series of pulses at the output terminal. Each of the voltage sources may be a programmable digital-to-analog converter receiving a voltage control signal and generating a voltage based on the voltage control signal.

Abstract: A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.

Abstract: A flat-panel field emission display comprises a luminescent faceplate, a rigid backplate, and an interposed or sandwiched emitter or cathode plate. A positioning spacer or connector ridge is formed on the rear surface of the faceplate to space the cathode plate a fixed distance behind the faceplate. A peripheral seal is formed between the faceplate and the backplate. The faceplate, backplate, and peripheral seal define an evacuated internal space which contains the cathode plate. The backplate is spaced behind the cathode plate to create a rearward vacuum space in which a getter is located.

Abstract: An integrated circuit includes a first conductive layer, an insulator layer disposed on the first conductive layer, and a second conductive layer disposed on the insulator layer. A first fuse is disposed in the first conductive layer and provides a first signal, and a second fuse is disposed in the second conductive layer in alignment with the first fuse and provides a second signal.

Abstract: The present invention provides suspensions and methods for depositing luminescent materials (e.g., phosphors) using electrophoresis, particularly during the preparation of display devices, such as field emission display devices, and the articles produced thereby. The luminescent material is deposited onto a substrate having thereon a metal-containing transparent, conductive coating. The suspension includes a nonaqueous liquid, a luminescent material, and a salt of a metal of the transparent, conductive coating.

Abstract: An improved apparatus and method for manufacturing semiconductor devices, and, in particular, for depositing material at the bottom of a contact hole, comprises sputtering a material onto a semiconductor substrate; applying a first bias voltage to the substrate, simultaneously removing the material surrounding the contact hole to form a facet at the top of the recess; and applying a second bias voltage to the substrate, simultaneously sputter-depositing the first material onto the bottom of the recess. A further embodiment of the invention utilizes an electrically isolated collimator for the sputtering apparatus. Another embodiment of the invention resputters a first material onto sidewalls of a contact hole during physical vapor deposition.

Abstract: Wireless communication devices and methods of forming the same are described. In one implementation, an integrated circuitry transceiver chip and an antenna are operably coupled and mounted within a housing member. A cover(s) is (are) disposed over the chip and antenna and effectively seals the chip and antenna therewithin. In a preferred implementation, the chip, antenna, and a power source are mounted on a printed circuit substrate which is nestedly received by the housing member and effectively sealed therewithin by the cover. The housing member preferably includes structure which receives at least one of the chip and/or power source to provide a nested, compact device which can be carried by or upon a person. In one aspect, the housing member is formed from a material which does not meaningfully, if at all, degrade the electrical performance of the device. The cover(s) is preferably formed from the same material as the housing member to facilitate assembly of the device through bonding therebetween.