Abstract: One embodiment of the present invention provides a system which selectively executes deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution. During normal-execution mode, the processor issues instructions for execution in program order. When the processor encounters a long-latency operation, such as a load miss, the processor records the long-latency operation in a long-latency scoreboard, wherein each entry in the long-latency scoreboard includes a deferred buffer start index. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred into a deferred buffer, and wherein other non-deferred instructions are executed in program order.

Abstract: Embodiments of the present invention provide for execution of a protocol in a multi-processor network device. In one embodiment, a hash function is applied to one or more fields of the data packet header to determine a unique index. A hash table is then queried, whereby data indicating one or more threads corresponding to said unique index is extracted. An available thread of execution, which has previously handled packet in the same receive stream, may thus be selected from a pool of threads. The selected thread of execution is then dispatched to provide for receive processing of the present data packet.

Abstract: One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an external frequency signal from a neighboring chip. The system then compares the internal frequency signal with the external frequency signal to generate a control signal, which is applied to the local chip to adjust the operating speed of the local chip, and applied to the internal oscillator to adjust the frequency of the internal oscillator.

Abstract: A traffic management processor includes a departure time calculator for generating a departure time for each packet, a departure time table having a plurality of rows, each having a first portion for storing the departure time for a corresponding packet and having a second portion for storing a rollover bit, and a reset circuit configured to reset the rollover bits in a predetermined time.

Abstract: One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a short-latency scoreboard that delays issuance of instructions that depend upon uncompleted short-latency instructions. During operation, the system issues instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a condition (a launch condition) during an instruction (a launch-point instruction), which causes the processor to enter the speculative-execution mode, the system generates a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and commences execution in the speculative-execution mode.

Abstract: An address book API according to the present invention includes an abstracted API and one or more address book specific adapters. The abstracted API provides functionalities common to a plurality of address book programs. The abstracted API is abstract enough to readily interface with various address books. Each adapter provides for address book program specific implementation of functionalities.

Abstract: An electronics module comprises a housing; and a plurality of electronic and electrical components for example fans. The module includes electromagnetic shielding for example perforated panels side walls etc. that is associated with the housing and/or the electronic components, and which provides a Faraday cage for the electronic components. The shielding is constructed so that one or more of the components can be removed from the module while the module is in operation substantially without affecting the integrity of the Faraday cage. The module enables certain components thereof to be replaced without adding to the downtime of the system or increasing electromagnetic interference.

Abstract: A computer system may include one or more modules coupled to a backplane in a housing. A module support structure may allow cooling air to flow upwardly across the modules. In one embodiment, a power section of the module may be located downstream of a data section of the module. In another embodiment, offset brackets may hold a circuit board of a module at an offset relative to a pair of guides in a module support structure. In another embodiment, a heat sink may be coupled between heat producing components on a pair of adjacent modules. In another embodiment, a converter apparatus may support a plurality of modules in a different number of slots in a system. In another embodiment, a heat sink on a module may include a pair of heat pipes arranged such that the heat pipes diverge from one another toward the condenser ends of the heat pipes.

Abstract: A content addressable memory (CAM) device including a CAM array, encoding circuit, address circuit and error checking circuit. The encoding circuit generates an address value that corresponds to one of a plurality of match lines included within the CAM array. The address circuit receives the address value from the encoding circuit and enables a data word to be output from a CAM array storage location indicated by the address value. The error checking circuit receives the data word output from the storage location and determines whether the data word contains an error.

Abstract: A system in a package (SIP) or multi-chip module (200, 300, 400) (MCM) uses an electron beam (235, 335, 435) for electrically coupling between microcircuits (230, 330, 430) and (232, 332, 432). In one embodiment, the micro-circuits (230, 430) and (232, 432) can be configured in a side-by-side configuration. In another embodiment, the micro-circuits (330) and (332) can be configured in a chip-on-chip configuration. In yet another embodiment, the electron beam (435) can include a plurality of electron beams (436) and appear as ribbon shaped between two micro-circuits (430, 432). Further, the fabrication to form the electron source (234, 334, 434) and the deflector (261, 356, 461) can be at the final metallization step of the process.

Abstract: A technique for offsetting an orientation of signal lines in a printed circuit board involves rotating the printed circuit board prior to or as the signal lines are fabricated in the printed circuit board. Such offsetting results in a printed circuit board in which the signal lines are not orthogonal with an arrangement of woven glass fibers formed in the printed circuit board.

Abstract: In a computer network system, a command line interface system is described having a text-based browser for browsing details of host devices coupled to the network. The command line interface system data includes logic to monitor and manage network devices by allowing a user to traverse the network using text-based commands to view hierarchy and topology information of the network and the hosts. The command line interface browsing system advantageously ensures a command status state change in one hierarchy level of the host device being browsed is retained and communicated to other hierarchy levels as the user browses the network.

Abstract: A system and method for cooling electronic components. The system includes a surface. One or more electronic components are coupled to the surface, the one or more electronic components including an integrated circuit in contact with a heat sink. A blower is coupled to the surface, the blower having a first port, a second port, and an impeller that rotates around an axis. The blower is oriented such that the axis is perpendicular to the surface and non-intersecting with the heat sink, wherein the blower moves air across the heat sink.

Abstract: Embodiments of a system and method for using mobile agents for managing distribution of content in peer-to-peer networks. An initiating peer node may launch a mobile agent including an itinerary of a group of peer nodes configured to receive and share content from a distributor. The mobile agent may visit the peer nodes on the itinerary to search for and collect information on distributor content stored on the visited peer nodes. The mobile agent may return the payload to the initiating peer node after completing the itinerary. In one embodiment, the mobile agent may include authentication information, and each visited peer node may access the authentication information to verify the mobile agent as authorized by the distributor. The initiating peer node may examine the information provided by the mobile agent to detect unauthorized copies of the distributor content.

Abstract: A method for conveying a security context, including creating and assigning a virtual address to a client process, issuing a first Internet Protocol version compliant packet wherein the first Internet Protocol version compliant packet comprises a security context, prepending an issued packet with a second Internet Protocol version header producing a second Internet Protocol version compliant packet, forwarding the second Internet Protocol version compliant packet to a recipient, stripping away the second Internet Protocol version compliant header from the second Internet Protocol version compliant packet producing a stripped packet at the recipient, decrypting and authenticating the stripped packet using a particular method as indicated by the security context producing a decrypted and authenticated packet, and routing the decrypted and authenticated packet to a recipient process using the virtual address.

Abstract: A computer network may include one or more systems coupled to many components. The computer network may be a storage network that includes one or more systems connected to one or more storage systems. One or more components coupled to the computer network may be modular components such as field replaceable units (FRUs). A component may include a non-volatile memory that stores a value for an operational parameter of the component. The value for the operational parameter may specify an operating condition for the component. A monitor may be coupled to the component and may be configured to access the operational parameter value on the nonvolatile memory to determine if the component is operating outside of the specified operating condition.

Abstract: Disclosed is a method and circuit for generating an average binary code from at least two input binary codes. The circuit may be employed in an integrated circuit having first and second circuits for generating binary codes am-1:0 and bm-1:0, respectively. In one embodiment, the circuit asynchronously generates a binary code cm-1:0 representing an average of the binary codes am-1:0 and bm-1:0 generated by the first and second circuits, respectively.

Abstract: A device couples energy from an electromagnetic wave to charged particles in a beam. The device includes a micro-resonant structure and a cathode for providing electrons along a path. The micro-resonant structure, on receiving the electromagnetic wave, generates a varying field in a space including a portion of the path. Electrons are deflected or angularly modulated to a second path.

Abstract: An apparatus and method for controlling and providing a robust, single entry cache memory is described in connection with an on-board cache memory integrated with a microprocessor. By implementing the single entry cache memory in a redundancy array of the cache memory, CPU debug procedures may proceed independently of the cache debug by disabling part of the cache memory and enabling a dedicated single entry cache in the redundancy array. Use of a cache redundancy array for the single entry cache imposes no area or latency penalties because the existing cache redundancy array already matches the latency of the cache.

Abstract: Disclosed are apparatus and methods for controlling execution of a target software component within an isolated execution unit. In general terms, an intermediary software component is introduced within the isolated execution unit. This intermediary component program can initialize the isolated execution unit, and then start a target software component within the isolated execution unit. The intermediary component also establishes communication back to the parent (e.g., using an inter isolation communication). The intermediary component communicates with the target software component using the target component's unchanged API and mediates the communication back to the parent using the established inter isolation communication.