Patents Assigned to Microsystems, Inc.
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Patent number: 7231523Abstract: One embodiment of the present invention provides a method for facilitating secure extension of an application. The method operates by first establishing an agreement between an owner of the application and a third party to allow the third party to incorporate an extension into the application. Once an agreement has been established, the system causes the extension to be digitally signed with a private key associated with the owner of the application, whereby the resulting digital signature can be verified with a corresponding public key to confirm that the extension is authorized to be used by the application. The system also configures the application to operate with extensions signed with the private key. In a variation on this embodiment, causing the extension to be digitally signed involves receiving the extension from the third party and signing the extension with the private key belonging to the owner of the application.Type: GrantFiled: September 2, 2003Date of Patent: June 12, 2007Assignee: Sun Microsystems, Inc.Inventor: Bernd J. W. Mathiske
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Patent number: 7231635Abstract: A method of operating a computer system includes providing a program in memory, verifying the program prior to an installation of the program and generating a program fault signal when the verification fails. The program includes at least one program unit, and each program unit includes an Application Programming Interface (API) definition file and an implementation. Each API definition file defines items in its associated program unit that are made accessible to one or more other program units and each implementation includes executable code corresponding to the API definition file. The executable code includes type specific instructions and data. Verification includes determining whether a first program unit implementation is internally consistent, determining whether the first program unit implementation is consistent with a first program unit API definition file associated with the first program unit implementation and generating a program fault signal when the verifying fails.Type: GrantFiled: September 12, 2003Date of Patent: June 12, 2007Assignee: Sun Microsystems, Inc.Inventor: Judith E. Schwabe
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Patent number: 7231550Abstract: A method for managing a fault involves detecting an error, gathering data associated with the error to generate an error event, and categorizing the error event using a hierarchical organization of the error event.Type: GrantFiled: October 31, 2003Date of Patent: June 12, 2007Assignee: Sun Microsystems, Inc.Inventors: Cynthia A. McGuire, Michael W. Shapiro, Andrew M. Rudoff, Emrys J. Williams
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Patent number: 7231455Abstract: A system and method for throttling transmissions of gathered computer system monitoring and asset data within a customer's communications network. A relay is provided within the network with an interface for transmitting messages to a downstream device such as the Internet. A data transmission throttle controls the downstream interface to transmit data at or below a data transfer threshold defining an allowable data transfer volume per transmission period. The method includes receiving customer input and modifying the data transfer threshold based on the input, with thresholds being set for a matrix of transmission periods (such as 24 hour by 7 day). The data transmission throttle determines whether messages exceed thresholds for the current transmission period, such as by comparing the size of the message to a data flow counter, and controls data transmissions by the relay to not exceed the threshold and by resetting the counter for each threshold.Type: GrantFiled: June 25, 2002Date of Patent: June 12, 2007Assignee: Sun Microsystems, Inc.Inventors: Richard Marejka, Dean Kemp
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Patent number: 7231634Abstract: A method for analyzing memory after a system panic to identify scope and cause of memory corruption. The method includes retrieving a memory image for a computer system and identifying a data structure in the memory image that caused the panic. A rule set for the identified data structure is selected and applied to the memory image to determine a scope of the memory corruption. The method includes identifying data structures in the memory that are related to the identified data structure by type, structure, content, or location and applying the rule set to this subset of data structures. The method may include generating the rule set for the identified data structure and then validating the created rule set such as by applying it to data structures that are known to be uncorrupted. The corrupted data structures are then processed to determine a cause of the corruption.Type: GrantFiled: September 17, 2002Date of Patent: June 12, 2007Assignee: Sun Microsystems, Inc.Inventor: John M. Harres
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Patent number: 7231338Abstract: A distributed simulation system is provided in which timesteps may be divided into a first phase (referred to as the zero time phase herein) and a second phase (referred to as the real time phase herein). In the first phase, each distributed simulation node in the system may process one or more received commands without causing the simulator to evaluate the model in that distributed simulation node. In the second phase, each distributed simulation node may cause the simulator to evaluate the model in response to a command supplying one or more signal values to the model. In one embodiment, the second phase may iterate the evaluation of the model for each command received which supplies signal values. Each iteration may optionally include transmitting a command including the output signal values produced by the model during that iteration.Type: GrantFiled: November 9, 2001Date of Patent: June 12, 2007Assignee: Sun Microsystems, Inc.Inventors: Carl Cavanagh, Steven A. Sivier, Carl B. Frankel, James P. Freyensee
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Patent number: 7231417Abstract: A method of generating a function, the function for assessing a parameter. The method includes: displaying a field for receiving a rule on a computer; entering a rule into the computer; transmitting the rule to a server; storing the rule on the server; and generating a function for assessing the parameter.Type: GrantFiled: April 25, 2001Date of Patent: June 12, 2007Assignee: SUN Microsystems, Inc.Inventors: Ezhilan Narasimhan, Patric Chew Pok Chang
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Patent number: 7230840Abstract: A content addressable memory (CAM) device having a plurality of CAM blocks and a block selection circuit. Each of the CAM blocks includes an array of CAM cells to store data words having a width determined according to a configuration value. The block selection circuit includes an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each of the select signals selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to whether the class code matches a class assignment of the CAM block.Type: GrantFiled: October 12, 2004Date of Patent: June 12, 2007Assignee: NetLogic Microsystems, Inc.Inventors: Jose P. Pereira, Varadarajan Srinivasan
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Patent number: 7231376Abstract: One embodiment of the present invention provides a system that performs high-level parallelization of large scale quadratic-problem (QP) optimization. During operation, the system receives a training dataset comprised of a number of data vectors. The system first determines to what extent each data vector violates conditions associated with a current support vector machine (SVM). The system then sorts the data vectors based on each data vector's degree of violation. Next, the system partitions the sorted data vectors into a number of prioritized subsets, wherein the subset with the highest priority contains the largest number of violators with the highest degree of violation. The system subsequently solves in parallel a QP optimization problem for each subset based on the subset's priority. The system then constructs a new SVM to replace the current SVM based on the QP optimization solution for each subset.Type: GrantFiled: April 21, 2005Date of Patent: June 12, 2007Assignee: Sun Microsystems, Inc.Inventors: Filiz Gurtuna, Aleksey M. Urmanov, Kenny C. Gross
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Publication number: 20070130387Abstract: A method for executing input/output (I/O) operations based on priority involves receiving a first I/O request for a unit of data, receiving a second I/O request for the same unit of data, determining a priority of the first I/O request and a priority of the second I/O request, and executing the first I/O request based on priority, where the first I/O request is executed based on the higher of the priority of the first I/O request and the priority of the second I/O request.Type: ApplicationFiled: May 12, 2006Publication date: June 7, 2007Applicant: Sun Microsystems, Inc.Inventors: William Moore, Jeffrey Bonwick
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Patent number: 7228378Abstract: A method for performing a search in a content addressable memory (“CAM”) device comprising comparing a search key with compound entries in a CAM array, wherein at least one of the compound entries includes (i) a ternary CAM word having a data word and a mask word, and (ii) a mask specifier that indicates the state of the mask word, and wherein the search key includes (i) a search word component, and (ii) a search mask component, and wherein the ternary CAM word is compared with the search word and the mask specifier is compared with the search word component; and generating a match signal associated with an compound entry that matches the search key.Type: GrantFiled: February 27, 2004Date of Patent: June 5, 2007Assignee: NetLogic Microsystems, Inc.Inventor: Jose P. Pereira
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Patent number: 7227424Abstract: In various embodiments, the invention provides a frequency controller and a temperature compensator for frequency control and selection in a clock generator and/or a timing and frequency reference. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals.Type: GrantFiled: March 21, 2005Date of Patent: June 5, 2007Assignee: Mobius Microsystems, Inc.Inventors: Michael Shannon McCorquodale, Scott Michael Pernia
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Patent number: 7228533Abstract: Techniques for generation of Java macro instructions suitable for use in Java computing environments are disclosed. As such, the techniques can be implemented in a Java virtual machine to efficiently execute Java instructions. As will be appreciated, a Java macro instruction can be substituted for two or more Java Bytecode instructions. This, in turn, reduces the number of Java instructions that are executed by the interpreter. As a result, the performance of virtual machines, especially those operating with limited resources, is improved. A Java macro instruction can be generated for conventional Java instruction sequences or sequences of Java instruction that are provided in a reduced set of instruction. In any case, sequences that are frequently encountered can be replaced by a Java macro instruction. These sequences are typically encountered when Java objects are instantiated, during programming loops, and when a local variables are assigned a value.Type: GrantFiled: August 24, 2001Date of Patent: June 5, 2007Assignee: Sun Microsystems, Inc.Inventor: Stepan Sokolov
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Patent number: 7227423Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant frequency in response to fabrication process variation. In addition, the various embodiments may also include a frequency divider adapted to divide the first signal having the resonant frequency into a plurality of second signals having a corresponding plurality of frequencies substantially equal to or lower than the resonant frequency; and a frequency selector adapted to provide an output signal from the plurality of second signals.Type: GrantFiled: March 21, 2005Date of Patent: June 5, 2007Assignee: Mobius Microsystems, Inc.Inventors: Michael Shannon McCorquodale, Scott Michael Pernia, Amar Sarbbasesh Basu
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Patent number: 7228474Abstract: A semiconductor device includes at least one component which is vulnerable to damage during scan testing for a particular input data configuration, and supports a safe mode in which this particular input data configuration is disabled. The semiconductor device also includes a port for receiving an input scan vector for scan testing, and an authorization unit connected to said port. The authorization unit maintains the device in safe mode if an input scan vector does not satisfy at least one predetermined criterion. In one particular implementation, the authorization unit generates a digital signature for the input scan vector, which is then compared to a signature portion included within the input scan vector itself. Scan testing is enabled providing that this comparison finds a match.Type: GrantFiled: January 7, 2003Date of Patent: June 5, 2007Assignee: Sun Microsystems, Inc.Inventors: Emrys Williams, Kenneth Alan House, Joseph Raymond Siegel
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Patent number: 7228532Abstract: One embodiment of the present invention provides a system that facilitates code verification and garbage collection in a platform-independent virtual machine. The system operates by first receiving a code module written in a platform-independent language. Next, the system examines the code module to locate calls to program methods within the code module. The system then transforms the code module so that all operands remaining on the evaluation stack only relate to the called method when the method is called, thereby simplifying verification and garbage collection of the code module.Type: GrantFiled: June 24, 2003Date of Patent: June 5, 2007Assignee: Sun Microsystems, Inc.Inventors: Nicholas Shaylor, Douglas N. Simon
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Patent number: 7227748Abstract: A cooling module is provided for an electrically powered apparatus. The cooling module comprises a non-volatile memory arranged to store a module identifier code for the module.Type: GrantFiled: March 31, 2003Date of Patent: June 5, 2007Assignee: Sun Microsystems, Inc.Inventor: Paul Jeffrey Garnett
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Patent number: 7228458Abstract: Methods are provided for testing storage devices and related devices for use in a clustered system. Storage devices may be pre-qualified before cluster software is installed for controlling the clustered system. Some implementations allow one or more storage devices in a cluster to be automatically tested in a variety of fault and non-fault scenarios.Type: GrantFiled: December 19, 2003Date of Patent: June 5, 2007Assignee: Sun Microsystems, Inc.Inventor: Ambujavalli Kesavan
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Patent number: 7228324Abstract: A floating point max/min circuit for determining the maximum or minimum of two floating point operands includes a first analysis circuit configured to determine a format of a first floating point operand of the two floating point operands based upon floating point status information encoded within the first floating point operand, a second analysis circuit configured to determine a format of a second floating point operand of the two floating point operands based upon floating point status information encoded within the second floating point operand, a decision circuit, coupled to the first analysis circuit and to the second analysis circuit and responding to a function control signal that indicates the threshold condition is one of a maximum of the two floating point operands and a minimum of the two floating point operands, for generating at least one assembly control signal based on the format of a first floating point operand, the format of a second floating point operand, and the function control signal,Type: GrantFiled: December 28, 2001Date of Patent: June 5, 2007Assignee: Sun Microsystems, Inc.Inventor: Guy L. Steele, Jr.
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Patent number: D543830Type: GrantFiled: July 12, 2006Date of Patent: June 5, 2007Assignee: Sun Microsystems, Inc.Inventors: Christopher H. Frank, Frank M. Miyahira