Abstract: A method for provisioning a plurality of heterogeneous operating systems on a plurality of target hosts that includes for each of the plurality of target hosts, obtaining a type of operating system (OS) to be provisioned on the target host, populating an OS profile model based on the type of operating system obtained, activating a deployment service based on the type of operating system, and provisioning the target host using a deployment service and the OS profile model.
Type:
Application
Filed:
November 23, 2005
Publication date:
May 24, 2007
Applicant:
Sun Microsystems, Inc.
Inventors:
Prashant Jamkhedkar, Ravi Chitloor, Amresh Prasad, Anand Bhalerao, Pierre Couture, Ushasree Kode
Abstract: In general, embodiments of the invention relate to a disk, which includes a plurality of files and rectory associated with the plurality of files comprising a plurality of directory entries. Further, each of the plurality of directory entries is associated one of the plurality of files and each of the plurality of directory entries is associated with a collision differentiator (CD). In one aspect of the invention, a hash value calculated for each of the plurality of directory entries is used to determine the CD associated with each of the plurality of directory entries.
Abstract: A system includes a Scalable Vector Graphics (SVG) image for representing at least one portion of a consumer electronic device and a scaler for scaling the SVG image to obtain a scaled SVG image where a display size of the scaled SVG image equals a predefined physical size of the at least one portion of the consumer electronic device where the SVG image is defined by an SVG tag.
Abstract: A reference timing architecture is disclosed that provides a level of flexibility that was not available with the architecture in the prior art. In particular, the present invention provides for multiple reference timing outputs that can be routed to equipment nodes relying on the timing information, wherein each of the timing processing paths that provide timing outputs can be controlled independently of one another.
Abstract: Embodiments of a decentralized, distributed trust mechanism that may be used in various networking platforms including peer-to-peer platforms, to implement trust relationships between and among nodes on a network and to implement trust relationships between nodes and content and data (codat). Protocols and methods may be provided for determining, disseminating and updating trust. For participating nodes, trust may be biased towards data relevance. Trust may have multiple components or factors, which may include node confidence, codat confidence and risk components, and embodiments may provide for the inclusion of factors of trust based on groups of nodes' common interests and/or group content relevance. Embodiments may be used for a variety of applications in which trust may be based on the norm for social interaction between participating nodes.
Abstract: A versioning Application Programming Interface (API) is provided for a software platform based on an object-oriented platform-independent programming language. The versioning API includes (a) main interfaces defining versioning functionality, the main interfaces allowing access to the versioning functionality, (b) a functional implementation of the main interfaces, the functional implementation including classes and libraries implementing the versioning functionality, the classes including a reference to a program module to perform a requested versioning function, and (c) a user interface for using the versioning functionality. The versioning API may further include native programming interfaces allowing code written in the object-oriented platform-independent language to operate with code written in a native language other than the object-oriented platform-independent language. The classes and some libraries are written in an object-oriented platform-independent programming language.
Abstract: One embodiment of the present invention provides a system for solving a system of equations in fixed-point form. During operation, the system receives a representation of the equations in fixed-point form and stores the representation a computer memory. Next, the system reduces the dimension of the system of equations, when possible, by eliminating variables in the system of equations to produce a reduced system of equations. The system then performs interval intersections based on the Fixed Point theorem to reduce the size of a box containing solutions to the reduced system of equations. In a variation on this embodiment, the system additionally applies interval techniques to find solutions to the system of equations, when such solutions exist.
Abstract: A pseudo ternary content addressable memory (PTCAM) device (100) can include a number of PTCAM blocks (102-0 to 102-63), each of which can include a number of standard PTCAM rows (106-0 to 106-63) and a standard memory row (104-0 to 104-63) for storing and providing mask information for the PTCAM rows. Redundancy for replacing a defective standard PTCAM row can be provided by a redundant section (108) that include fewer PTCAM rows than in a PTCAM block (102-0 to 102-63). Non-defective PTCAM rows within a standard PTCAM block containing a defective PTCAM row can continue to operate.
Abstract: Linking a virtual method comprises receiving a program comprising multiple program units, enumerating classes of the program, determining whether a virtual method of the program has been overridden at least once, creating a virtual method jump table indexed by a type indicator if the virtual method has been overridden and rewriting at least one call instruction that calls the virtual method. The at least one call instruction is rewritten to include the type indicator of a called object. The table comprises at least one entry including an address of a virtual method.
Abstract: A scheduler may be configured to schedule a plurality of blocks of concurrent code for multi-threaded execution. The scheduler may be configured to initiate multi-threaded execution of the blocks of concurrent code in an order determined by block-level performance criteria for the blocks of concurrent code to reduce overall execution time of the concurrent code. In one embodiment, the scheduler may be configured to schedule code blocks having a longer run time ahead of blocks having a shorter run time. The scheduler may be configured to schedule a group of said blocks based on a goal of each of the blocks of the group completing execution at approximately the same time. The scheduler may also be configured to initiate multi-threaded execution of each block of the group at different times according to the block-level performance criteria to the goal.
Type:
Grant
Filed:
October 22, 2002
Date of Patent:
May 22, 2007
Assignee:
Sun Microsystems, Inc.
Inventors:
Bala Dutt, Ajay Kumar, Hanumantha R. Susarla
Abstract: One embodiment of the present invention provides a system that facilitates performing exception-free arithmetic operations within a computer system. During execution of a computer program, the system receives an instruction to perform an arithmetic operation that involves manipulating floating-point values. If the arithmetic operation manipulates a floating-point value representing {+0}, the arithmetic operation is performed in a manner consistent with {+0} representing a set containing a single value “?0”, wherein “?0” is the limit of a sequence of values that approaches zero only from above. Similarly, if the arithmetic operation manipulates a floating-point value representing {?0}, the arithmetic operation is performed in a manner consistent with {?0} representing a set containing a single value “+0”, wherein “+0” is the limit of a sequence of values that approaches zero only from below.
Abstract: A range check elimination loop structure is provided. The range check elimination loop structure includes a pre-loop structure based on an original loop structure, where the pre-loop structure is capable of testing indexing expressions for underflow. In addition, a main loop structure having indexing expressions based on the original loop structure is included. The indexing expressions included in the main loop preferably cannot produce an underflow or an overflow. Also included in the range check elimination loop structure is a post-loop structure based on the original loop structure that is capable of testing indexing expressions for overflow.
Type:
Grant
Filed:
May 31, 2001
Date of Patent:
May 22, 2007
Assignee:
Sun Microsystems, Inc.
Inventors:
Clifford N. Click, Christopher A. Vick, Michael H. Paleczny
Abstract: A field-replaceable active pumped liquid heat sink module includes a front portion and a back portion, each including a liquid pump, a radiator, an optional receiver, and a cold plate heat exchanger, all of which are connected together in a liquid pump loop through which a coolant such as water is circulated. The liquid pump, radiator, optional receiver and cold plate heat exchanger are in a liquid pump loop and are self-contained in a field-replaceable active pumped liquid heat sink module.
Abstract: A multiprocessor computer system is configured to selectively transmit address transactions through an address network using either a broadcast mode or a point-to-point mode transparent to the active devices that initiate the transactions. Depending on the mode of transmission selected, either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency within the system. A computing node is formed by a group of clients which share a common address and data network. The address network is configured to determine whether a particular transaction is to be conveyed in broadcast mode or point-to-point mode. In one embodiment, the address network includes a mode table with entries which are configurable to indicate transmission modes corresponding to different regions of the address space within the node.
Abstract: A method for modifying a directory entry, which includes receiving a request to modify the directory entry, determining whether a directory entry lock associated with the directory entry is present, instantiating the directory entry lock, if the directory entry lock associated with the directory entry is not present, waiting until the directory entry lock is released, if the directory entry lock is present, providing the directory entry lock to a caller of the request, placing an entry corresponding to the directory entry lock on a dynamic lock list associated with the directory, processing the request by the caller, releasing the directory entry lock once the request has been processed, and removing the entry corresponding to the directory entry lock from the dynamic lock list.
Abstract: A method for testing an intent log for a file system that includes creating a first file system, issuing a command to freeze the first file system, performing a plurality of commands on the first file system to obtain a plurality of deltas, wherein each of the plurality of deltas is stored in the intent log and is not committed to the first file system, copying the first file system to obtain a second file system, committing each of the plurality of deltas in the intent log to the second file system, unfreezing the first file system and committing each of the deltas in the intent log to the first file system, and comparing the first file system, after committing each of the deltas in the intent log, to the second file system to determine whether the intent log is valid.
Abstract: A method for backing up a file system, including obtaining a first indirect block comprising a first block pointer, obtaining a first birth time from the first block pointer, determining whether the first birth time is subsequent to a time of a last backup, and backing up a first block referenced by the first block pointer, if the first birth time is subsequent to the time of the last backup.
Abstract: A system for debugging applications at resource-constrained virtual machines may include a target device configured to host a lightweight debug agent to obtain debug information from one or more threads of execution at a virtual machine executing at the target device, and a debug controller. The lightweight debug agent may include a plurality of independently deployable modules. The debug controller may be configured to select one or more of the modules for deployment at the virtual machine for a debug session initiated to debug a targeted thread, to deploy the selected modules at the virtual machine for the debug session, and to receive debug information related to the targeted thread from the lightweight debug agent during the session.
Abstract: An extensible fingerprint comprised of an ordered list of fingerprints generated by applying each of a plurality of distinct fingerprinting functions to the content of a data item. The extensible fingerprint can be extended by using a new fingerprinting function to compute a new fingerprint and adding the new fingerprint to the list so that the old extensible fingerprint of a data item is used as a prefix of the new extensible fingerprint for that data item. Thus, the fingerprint can be incrementally extended over time. A content-addressed storage system uses extensible fingerprints as addresses and can also change over time.
Abstract: Computing an output interval includes producing a first product resulting from a conditional multiplication using a first operand, a second operand, and a third operand. Next a second product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Then a third product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. Next a fourth product is produced resulting from the conditional multiplication using the first operand, the second operand, and the third operand. And finally, the output interval is produced including an output interval lower-point and an output interval upper-point, the output interval lower-point being the minimum of the first product and the third product, and the output interval upper-point being the maximum of the second product and the fourth product.