Abstract: Given two synchronous clocks which transact data from a transmitter element to a receiver element which are analyzed by static timing, the interval between the transmitting data launch clock edge and the receiving capture clock edge is adjusted from the clock waveforms provided in order to represent the worst case slack situation between these two clocks over time. The amount of this adjustment is determined without unrolling (enumerating) all possible launch/capture pairs for these clocks. The greatest common divisor (GCD) of a transmit clock frequency and a receive clock frequency is determined. An effective phase shift is determined by performing a MOD operation between the GCD and an offset of the transmitter and receiver clocks. An algorithm uses the GCD and effective phase shift to determine a launch/capture interval that corresponds to a critical slack condition.

Abstract: A low power circuit for providing power and control signals to a low noise block converter of a satellite receiver over a single coaxial cable includes a tracking switch-mode power supply. The power and control signals have a DC voltage level selected from a plurality of DC voltage levels and are modulated by an analog AC tone signal. The switch-mode power supply provides a regulated output voltage which tracks the selected DC voltage level. The regulated output voltage provides the input voltage to an adjustable linear amplifier which generates an output voltage having the selected DC voltage level modulated by the analog AC tone signal.

Abstract: Data stored within a cluster may be distributed among nodes each storing a portion of the data. The data may be replicated wherein different nodes store copies of the same portion of the data. In response to detecting the failure of a node, the cluster may initiate a timeout period. If the node remains failed throughout the timeout period, the cluster may copy the portion of the data stored on the failed node onto one or more other nodes of the cluster. If the node returns to the cluster during the timeout period, the cluster may maintain the copy of the data on the previously failed node without copying the portion of the data stored on the failed node onto any other nodes. By delaying self-healing of the cluster for the timeout period, an unbalanced data distribution may be avoided in cases where a failed node quickly rejoins the cluster.

Abstract: A method for distributing code resident on a remote application server to a local server. When a client requests information, a request handler on the local server handles the request. If the information is available on the local server, the request handler satisfies the request using this information. If the information is not available locally, the request handler accesses the remote application server to obtain the requested information. The request handler forwards the information to the client and caches it on the local server. Where the information cannot be transferred to the local application server, the request handler establishes a proxy to the remote application server that forwards a client request to the remote application server and a response from the remote application server to the client. The client communicates transparently with the remote application server via the proxy on the local application server.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide for exchanging messages directly between a client and a selected server regardless of the use of a load balancer. The client generates a message to bypass performing load balancing functionality at the load balancer, and sends the message to the load balancer. The load balancing functionality is bypassed and the message is sent directly to the selected server by the load balancer.

Abstract: A method of performing a fast information compare within a processor which includes performing a more significant bit compare when information is loaded into a translation lookaside buffer, storing a result of the more significant bit compare within the translation lookaside buffer as part of an entry containing the information, and using the result of the more significant bit compare in conjunction with results from a compare of less significant bits of the information and less significant bits of compare information to determine whether a match is present. The more significant bit compare compares more significant bits of the information being loaded into the translation lookaside buffer with more significant bits of compare information.

Abstract: A method of testing an embedded memory which includes providing a programmable memory built-in self-test module and using the programmable memory built-in self-test module to extract contents of the embedded memory upon detection of an error. The programmable memory built-in self-test module includes a pseudo binary search and stop on error function.

Abstract: The present invention provides private namespaces for active computing environments. The invention uses one or more “compute capsules”. A compute capsule is a private, portable, persistent environment. Each compute capsule comprises an arbitrary set of active processes and their associated state information. In one embodiment, compute capsules provide a private, customizable view of a shared file system, so that users can modify arbitrary files without the expense of providing each person with a separate and complete file system image. In one embodiment, the invention provides environments with different personalities, each of which can be contained within a capsule. For example, a user can have one capsule for normal desktop usage, a fail-safe capsule with a minimal environment and no external dependencies, capsules for work-related and personal activities, etc. In one embodiment, capsules are given access rights.

Abstract: A content addressable memory (CAM) (200) is disclosed that includes a value match mode, where a comparand value can be compared to a masked data value, and a range match mode where a comparand value can be compared to an upper range limit UR and a lower range limit LR. The CAM (200) may include a number of CAM cells (204-n to 204-0) that may each be connected to a compare section (109). A compare section (109) can include a first compare circuit (210) that may generate a match indication on a match line (212) and a second compare circuits (214-n to 214-0). A more significant second compare circuits (214-n) may provide upper and lower limit match results (UMn, LMn) to a less significant first compare circuit (210).

Abstract: A method for arithmetic expression optimization includes receiving an operator and at least one operand of a first instruction defined for a first processor having a first base. The method also includes converting the first instruction to a second instruction optimized for a second processor having a second base smaller than the first base when the at least one operand does not carry potential overflow beyond the second base or when the operator is insensitive to overflow. The method also includes converting instructions in an instruction chain to a wider base larger than the second base and smaller or equal to the first base when the at least one operand carries potential overflow beyond the second base and when the operator is sensitive to overflow. The chain is bounded by the second instruction and a third instruction that has been previously optimized and is the source of the potential overflow.

Abstract: A system and method for reducing the overhead involved in allocating memory to a task, thread or similar entity that shares memory or some other resource with other tasks or threads. A task is assigned a memory limit identifying a maximum amount of memory it may use at one time. When the task requires additional memory to store an object, it is granted a local allocation buffer if the size of the buffer plus the task's current memory allocation will not exceed the task's memory limit. Thereafter, memory space for objects is allocated from the task's local allocation buffer. This scheme avoids the overhead of constantly checking whether it has reached its limit, which is normally performed every time a task allocates memory. For large objects (e.g., greater in size than a local allocation buffer), memory may be allocated directly from the shared area.

Abstract: A system and method is provided to allow a computer network system to keep a device in a powered off state over a power cycle. A service processor stores the power state information or power mask corresponding to the field replaceable unit (FRU) slots in a non-volatile storage location. As a result, after the system has been powered off and on, the power mask information is retained. Accordingly, a hotswap controller may then retrieve the power mask from storage to determine whether a given FRU should be powered on or kept in a powered off state. Depending on the power mask, the service processor will not power on the FRU if the power mask indicates that the device should remain in a powered off state. A management entity may update the power mask information depending on predetermined parameters or the condition of the FRU. As a result, a power mask may be maintained for several power cycles to keep a device in a powered off state.

Abstract: A dynamic administration framework for server systems. A generation mechanism may generate one or more components of the administration framework from meta-information describing persistently stored configuration information. Components providing an in-memory representation of configuration information and components representing business logic of the server may be generated. A user interface may be generated which may be used to administer the generated components. A configuration API may be provided that provides a transparent interface to the persistent store, abstracting storage format and location from clients of the configuration API. A generated administration framework may be compiled with application server or system-specific components. The compiled system may then be used at runtime. One embodiment may include an event notification mechanism that may allow changes in configuration data to be propagated to one or more servers.

Abstract: Provided is a method and apparatus for registering requests to access physical memory in a physical address mapping framework. Specifically, a device can register in the physical address mapping framework before accessing physical memory, thus permitting an operating system to identify the device when it is necessary to relocate pages in physical memory. The physical address mapping framework can be any structure that permits registration. For example, the structure can be a list or a tree. When relocating physical memory, all accesses registered in the physical address mapping framework are restricted. Then, the device is notified to stop accessing physical memory via information stored in the physical address mapping framework. After the relocation, the device is notified to resume accessing physical memory via information stored in the physical address mapping framework.

Abstract: One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution are monitored to detect interfering accesses from other threads, and wherein changes made during transactional execution are not committed until transactional execution completes without encountering an interfering data access from another thread. Upon encountering a release instruction for a memory location during the transactional program execution, the system modifies state information within the processor to release the memory location from monitoring.

Abstract: Embodiments of a distributed index mechanism for indexing and searching for identity information in peer-to-peer networks. In one embodiment, a distributed index may be used to store identity information in a decentralized manner on a plurality of peer nodes. The identity information may be used, for example, to authenticate users. Distributed indexes may allow identity information to be spread across multiple peer nodes so that the load is spread among the various peer nodes. In one embodiment, the distributed index may be a distributed hash table. One embodiment of a distributed index of identity information may be implemented in peer-to-peer networks implemented according to a peer-to-peer platform including one or more peer-to-peer platform protocols for enabling peer nodes to discover each other, communicate with each other, and cooperate with each other to form peer groups and share network resources.

Abstract: A processor is defined by a new architectural feature called a Backing Register File, where a Backing Register File is a set of randomly accessible registers capable of holding values, and further are directly connected to the processor's register files. The processor's register files are in turn connected to the processor's execution units. A Backing Register File is visible and controllable by users, allowing them to make use of a larger local address space increasing execution unit throughput thereby, while not changing the size of the processor's register files themselves.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide for managing exposure to failure for computer-based systems. Information about a computer-based system is asynchronously received. An exposure level to failure of the computer-based system is calculated based on the received information. A stability of the computer-based system is determined based on the exposure level. A stability indication is output responsive to the determined stability.

Abstract: A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Output logic circuitry of the phase shift driver may generate an output signal at a second phase relative to the input signal. The output signal may be a phase-shifted version of the input signal. A reset control circuit may receive a feedback signal from the output logic circuitry and an intermediate signal from the input logic circuitry and generate a reset signal based on the received feedback and intermediate signals. The reset control circuit may control a pulse width of the reset signal to reset the input logic circuitry within a period of time before the input logic circuitry receives a subsequent input signal.

Abstract: A system and method for providing switch redundancy in a computer network comprises two or more separate servers that are connected together to allow the servers to operate as one complete system that may continue to operate even in the event that one server becomes unable to provide switching functions. In one exemplary embodiment, the computer network includes two or more servers and a server bridging assembly. Two or more servers are interconnected via the server bridging assembly such that, in the event that a switch located in one of the servers fails, the switch located in the other server can be used to provide switching functions for both servers. As a result, the servers are interconnected to provide redundancy.