Patents Assigned to Microsystems, Inc.
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Publication number: 20070089867Abstract: A heat sink is configured to cool at least one hot spot of an integrated circuit. The heat sink has a first pipe and a second pipe disposed interior to and concentric with the first pipe, where at least a portion of each of the first pipe and the second pipe is arranged to be disposed vertically over the hot spot. An assembly connected to the first pipe and the second pipe is arranged to generate a magnetic field and induce electrical current flow through the magnetic field. A flow of thermally and electrically conductive fluid in the first pipe and a flow of the fluid in the second pipe are dependent on the electrical current flow and the magnetic field.Type: ApplicationFiled: October 21, 2005Publication date: April 26, 2007Applicant: Sun Microsystems, Inc.Inventor: Chien Ouyang
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Patent number: 7210148Abstract: A homogeneous execution environment operates within a heterogeneous client-server network. A client selects a server and transmits a procedure call with parameters. In response, a server dynamically and securely downloads code to a compute server; invokes a generic compute method; executes the code on the compute server; and returns the results to the calling client method, preserving the result on the compute server if requested. This technique is efficient in that it does not require multiple copies of code to be downloaded or compiled since server byte-codes can be executed on each of the different systems, therefore downloading or compiling multiple copies of code can be avoided. The code can be compiled once and downloaded as needed to the various servers as byte-codes and then executed.Type: GrantFiled: March 16, 2001Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Kenneth C. R. C. Arnold, James H. Waldo, Ann M. Wollrath, Peter C. Jones
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Patent number: 7210066Abstract: A method for analyzing a test coverage of a software application specification by a test suite is provided. The method includes reading an assertion document for a specification. The assertion document has a corresponding tagged assertion for each assertion in the specification. Each tagged assertion is defined in a markup language. The method also includes reading a static file for defining tests of the test suite. The static file is defined in the markup language. The test suite is divided into tests and each test is divided into test cases. The static file is configured to include an entry for each test case and each entry is configured to include tagged assertions tested by the test case. Also included in the method is correlating each of the tagged assertions in the assertion document with the test cases in the static file so as to determine test coverage of the specification.Type: GrantFiled: December 31, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Ramesh Babu Mandava, Jean-Francois Arcand
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Patent number: 7210006Abstract: A read-to-write-back transaction may allow I/O subsystems (or other devices) to perform a write to a portion of a cache block without gaining ownership of the cache block and requiring that it respond to foreign requests for the cache block. In response to an I/O subsystem initiating a read-to-write-back transaction, the device owning the cache block conveys the cache block to the I/O subsystem, and the I/O subsystem may perform partial or entire writes to the cache block. Subsequently, the cache block is written back to a memory subsystem from the I/O subsystem. The system is implemented such that these operations may be viewed logically as an atomic operation with respect to other coherence transactions to the same cache block, and thus the I/O subsystem need not become the owner of the cache line during performance of the read-to-write-back transaction.Type: GrantFiled: June 30, 2003Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventor: Robert E. Cypher
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Patent number: 7210056Abstract: An Infiniband device can be provided. The device can comprise an input port having a serialiser/deserialiser. The serialiser/deserialiser can comprise: a data buffer for storing data from a received serial data stream and for outputting the stored data in parallel groups and a code detector for detecting a predetermined code pattern in the serial data stream and generating a code detection output in response thereto. The serialiser/deserialiser can also comprise a transition detector for detecting transitions in the serial data stream and reconstructing a serial data clock therefrom, and for generating a plurality of parallel data clocks from the serial data clock, each parallel data clock having a different phase. The data buffer can be responsive to the code detection output to adjust a parallel data group start position within the serial data stream and to cause a selection of one of the reduced frequency clocks having a phase corresponding to the adjusted parallel data group start position.Type: GrantFiled: June 8, 2004Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Magne Sandven, Brian Manula, Morten Schanke
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Patent number: 7210003Abstract: An apparatus and method for generating a comparand in a content addressable memory array. For one embodiment, the apparatus includes a content addressable memory (CAM) array and translation circuitry. The CAM array receives a comparand and the translation circuitry includes at least one first input, at least one second input, and at least one output. The first input is configured to receive an input data having a plurality of bit groups, wherein a first bit group has a first position in the input data relative to other bit groups. The second input is configured to receive translation information indicative of translation of the first bit group from the first position to a different position in a comparand. The output is coupled to the CAM array to transmit the comparand to the CAM array. For one example, the translation circuitry includes a switch circuit that may include one or more multiplexers or demultiplexers.Type: GrantFiled: October 31, 2001Date of Patent: April 24, 2007Assignee: Netlogic Microsystems, Inc.Inventors: Sandeep Khanna, Jose Pio Pereira, Sunder Raj Rathnavelu, Ronald S. Jankov
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Patent number: 7209960Abstract: A method and apparatus is provided for saving and loading Java applet data to and from, respectively, a local file system of a client computer system. It is not necessary to render the local file system accessible to the Java applet to save and load the Java applet data. Thus, the Java applet data is saved and loaded without compromising the security of the local file system and without requiring special certification of the Java applet.Type: GrantFiled: September 20, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventor: Pavel S. Veselov
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Patent number: 7209935Abstract: A garbage collector that employs the train algorithm to manage a generation in a computer system's dynamically allocated heap maintains for each of the generation's cars a respective remembered set that identifies all locations where references to objects in that car have been found by scanning locations identified by the mutator as having been modified. To avoid some of the expense of remembered-set updating, the collector refrains from attempting to add to a remembered set any reference located in a car that will be collected during the next collection increment. Additionally, if no mutator operation will occur before a collection set of one or more cars will be collected, any reference located outside that collection set but referring to an object within the collection set is not recorded in a remembered set but is recorded instead in a scratch-pad list of entries that identify references to collection-set objects that need to be evacuated.Type: GrantFiled: November 27, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventor: Alexander T. Garthwaite
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Patent number: 7210026Abstract: A processor includes a set of registers, each individually addressable using a corresponding register identification, and plural virtual registers, each individually addressable using a corresponding virtual register identification. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation. The processor can include a virtual register cache configured to store multiple sets of virtual register values, such that each of the multiple sets of virtual register values corresponds to a different context. Each of the plural virtual registers can include a valid bit that is reset on a context switch and set when a value is loaded from the virtual register cache. The processor can include a virtual register translation look-aside buffer for tracking the location of each set of virtual register values associated with each context.Type: GrantFiled: June 28, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventor: Peter C. Damron
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Patent number: 7209864Abstract: A method for testing performance of a constrained resources computing device (CRCD) is provided which includes determining that a data sample was generated and generating a time stamp corresponding to when the data sample was generated. The method also includes determining a defined time interval corresponding to the time stamp and incrementing a counter associated with the defined time interval corresponding to the time stamp.Type: GrantFiled: September 9, 2004Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Terrence Barr, David Proulx
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Patent number: 7209358Abstract: A computer system comprises a plurality of shelves. Each shelf has a carrier for removably receiving a plurality of information processing modules and a switching module. Each shelf also has an interconnection member for providing connections between the information processing modules and the switching module. The shelves are logically connected into a plurality of stacks, the switching modules of the respective shelves in each stack being interconnected in a logical stacking configuration. The computer system further comprises a shelf having a carrier for removably receiving a master switching module, wherein the master switching module is connected into each stack as a common master switch for all of the stacks.Type: GrantFiled: August 29, 2003Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Paul J. Garnett, Martin P. Mayhead, Thomas E. Giles, Ariel Hendel
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Patent number: 7209996Abstract: In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.Type: GrantFiled: October 16, 2002Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Leslie D. Kohn, Kunle A. Olukotun, Michael K. Wong
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Patent number: 7209981Abstract: A system is provided for switching the I/O channel for disk drives between multiple computers. The system incorporates the switch into removable drive modules, or a docking base for a removable drive module. The incorporation of switching into the system, such that it is integral with the drives, can reduce overall system failures, by reducing the number of elements which flow through a central switching element. Thus, even where a switch fails other drive modules of the system may continue to operate in the system and provide information to different computers of the system.Type: GrantFiled: January 9, 2004Date of Patent: April 24, 2007Assignee: Z Microsystems, Inc.Inventors: Jack P. Wade, Joel Brown
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Patent number: 7210121Abstract: A method for camouflaging a non-native application as a native application of a device is provided. The method includes generating a native code wrapper in a device dependent native code to handle a communication between a native operating system and the non-native application. The method further includes applying the native code wrapper to the non-native application generating a wrapped non-native application. The non-native application remains intact while in contact with the native code wrapper.Type: GrantFiled: June 9, 2003Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Bing Xia, Singyun Brian Chu
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Patent number: 7209939Abstract: A computer system for multiplying a first matrix and a second matrix that reduces rounding error, including a processor, a memory, a storage device, and software instructions stored in the memory for enabling the computer system, under the control of the processor, to perform obtaining a first set of dimension values for the first matrix and a second set of dimension values for the second matrix, selecting one of a plurality of multiplication permutations if the first set of dimension values and the second set of dimension values are greater than a crossover value, multiplying the first matrix by the second matrix using the multiplication permutation and a Strassen-Winograd method, recursively sub-dividing the first matrix and the second matrix producing a set of sub-matrix products and a recursion tree, and propagating the set of sub-matrix products up the recursion tree to produce a product matrix.Type: GrantFiled: February 10, 2003Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Rick R. Castrapel, John L. Gustafson
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Publication number: 20070085039Abstract: A device couples energy from an electromagnetic wave to charged particles in a beam. The device includes a micro-resonant structure and a cathode for providing electrons along a path. The micro-resonant structure, on receiving the electromagnetic wave, generates a varying field in a space including a portion of the path. Electrons are deflected or angularly modulated to a second path.Type: ApplicationFiled: October 5, 2005Publication date: April 19, 2007Applicant: Virgin Islands Microsystems, Inc.Inventors: Jonathan Gorrell, Mark Davidson, Michael Maines, Lev Gasparov, Paul Hart
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Patent number: 7207040Abstract: An invention is provided for affording thread priority control in a distributed computer system. At least one task is executed on a server, where each task includes a task identifier and a priority value. In addition, a change priority message, which includes priority value and a task identifier, is received over a network. In response, the priority value of a specific task having the same task identifier as the task identifier of the change priority message is set equal to the priority value of the change priority message. As a result, the specific task is executed at a priority level relative to the priority value of the specific task.Type: GrantFiled: August 15, 2002Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Konstantin I. Boudnik, Weiqiang Zhang
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Patent number: 7204701Abstract: A bolster plate apparatus, used to secure a semiconductor device intermediate a printed circuit board and a heat sink apparatus, includes either an indentation or an open aperture into which a radio frequency absorptive material may be disposed. The absorptive material may be a ferrite material specifically selected to absorb frequencies in the range of the second to fourth harmonic of the processor clock signal frequency. The type of the ferrite material implanted in the bolster plate is selected to maximize the absorption of radio frequency energy, particularly that emitted at the pad vias on the underside of the printed circuit board, without affecting the signal integrity of the other pad connections. The shape of the cutout or aperture is also defined by the arrangement of RF emitting pads on the underside of the printed circuit board.Type: GrantFiled: March 8, 2004Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Wigneswaran W. Balasingham, Istvan Novak, Robert S. Moffett, Daniel D. Gonsalves
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Patent number: 7206841Abstract: A system and method for providing rendezvous nodes in a peer-to-peer networking environment is described. Rendezvous nodes preferably cache information about network resources that may be useful to peer nodes on a peer-to-peer network. In one embodiment, a network of rendezvous nodes may help peer nodes to discover network resources over long-range on the peer-to-peer network. Network resource may include, but may not be limited to peer nodes, peer groups, services, content, and communication channels. In one embodiment, rendezvous nodes may respond to discovery query messages from peer nodes. The discovery query messages may specify desired network resource information. In one embodiment, rendezvous nodes may provide route discovery for network resources. In one embodiment, a peer node may be pre-configured with a pre-defined set of rendezvous nodes to access on startup. These bootstrapping rendezvous may help the peer node discover network resources that it needs to start up.Type: GrantFiled: January 22, 2002Date of Patent: April 17, 2007Assignee: Sun Microsystems, Inc.Inventors: Bernard A. Traversat, Li Gong, Mohamed M. Abdelaziz, Michael J. Duigou, Eric Pouyoul, Jean-Christophe Hugly, William N. Joy, Michael J. Clary
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Patent number: D541268Type: GrantFiled: September 8, 2005Date of Patent: April 24, 2007Assignee: Sun Microsystems, Inc.Inventors: Christopher H. Frank, Dimitry Struve, Jeffrey T. Paladini