Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and mixtures of the two have emerged recently. However, conventional debuggers do not provide features and capabilities that could be desirable for debugging programs executed using transactional memory. For example, conventional debuggers are not adapted to provide a coherent or consistent view of variables in a system that employs transactional memory. Because transactional memory implementations provide the “illusion” of multiple memory locations changing value atomically, while in fact they do not, there are challenges involved with integrating debuggers with such programs to provide the user with a coherent view of program execution.

Abstract: A method for configuration of a program with a plurality of configuration variables to operate on a computer system that includes obtaining a plurality of priority semantics for the plurality of configuration variables, wherein the plurality of priority semantics are heterogeneous, assigning a value for each of the plurality of configuration variables based on the plurality of priority semantics, and configuring the program using the value to operate on the computer system.

Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. Unfortunately, conventional debugging programs are often inadequate when employed in relation to code that employs transactional memory and new or modified techniques are needed. We describe techniques whereby certain facilities of a transactional memory implementation can be leveraged to provide replay debugging. With replay debugging, the user can examine a partial or complete execution of an atomic block after it has happened—for example, right before the execution commits. Moreover, in some cases the user can modify the replayed execution, and decide to commit the new modified execution instead of the original replayed one.

Abstract: A switch which is magnetic pole insensitive is described. The switch includes a Hall effect sensor coupled to a threshold circuit which provides an output signal indicative of the proximity of a magnet, and hence a magnetic field, to the Hall effect sensor regardless of the orientation of the magnet to the Hall effect sensor.

Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

Abstract: In one embodiment, a storage subsystem includes a plurality of storage arrays each including a plurality of storage devices. The storage subsystem also includes a plurality of array controllers each coupled to one or more of the plurality of storage arrays. One or more of the arrays corresponds to a failure group. Each array controller may create a storage volume including storage devices belonging to one or more of plurality of storage arrays. In addition, the storage subsystem includes a redundancy controller that may be configured to implement N+K redundancy. The redundancy controller includes configuration functionality that may determine a number of redundant system data blocks to be stored on different storage devices for a given stripe of data that is dependent upon particular values of N and K and upon physical system configuration information.

Abstract: An apparatus, system and method are provided for low-latency start-up of a free-running harmonic oscillator. The exemplary apparatus embodiment comprises a first and second current sources to generate first and second currents; a bias current monitor adapted to detect a magnitude of the second current and to provide a control signal when the magnitude of the second current is equal to or greater than a predetermined magnitude; and a bias controller adapted to switch the first current from the oscillator and to switch the second current to the oscillator in response to the control signal. a reference voltage generator, a comparator, and a bias controller. Exemplary embodiments include reference voltage generator, a comparator, and a bias controller.

Abstract: Embodiments may provide mechanisms for representing trust between peers or systems in decentralized networking environments including peer-to-peer networking environments. Trust may include both direct trust between two peers and trust in a pipeline of peers along which codat may be passed. Embodiments may provide a mechanism for a peer to represent and rate the trustworthiness of other peers as providers of codat relevant to the peer's interest. To evaluate trust in another peer as a provider of codats in the area of interest, trust may be represented with two components, confidence and risk. Embodiments may provide mechanisms for measuring the components and determining trust from the components. Embodiments may also provide mechanisms for feeding back trust information to the providing peer and for propagating trust information to other peers.

Abstract: Methods and systems consistent with the present invention provide a mechanism for accepting extended amounts of data in a layered network protocol. The methods and systems thus allow the network protocol to more efficiently receive data and forward the data to the correct entity. As a result, the programs experience greater network data throughput. The methods and systems may be implemented in widely accepted Internet Protocol (IP) and Transmission Control Protocol (TCP) networks.

Abstract: One embodiment of the present invention provides a system that supports concurrent accesses to a skip list that is lock-free, which means that the skip list can be simultaneously accessed by multiple processes without requiring the processes to perform locking operations. During a node deletion operation, the system receives reference to a target node to be deleted from the skip list. The system marks a next pointer in the target node to indicate that the target node is deleted, wherein next pointer contains the address of an immediately following node in the skip list. This marking operation does not destroy the address of the immediately following node, and furthermore, the marking operation is performed atomically and thereby without interference from other processes.

Abstract: A system and method for dynamically disabling partially streamed content may include a server receiving a request from a client. A session may be initiated or continued in response to the request. The server may begin to stream content to the client as a partial fulfillment of the request. While processing the request, the server may determine if the partially streamed content should be disabled. In response to determining that the partially streamed content should be disabled, the server may disable the partially streamed content without terminating the session. Disabling the partially streamed content may involve preventing the client from accessing content referenced by a hyperlink associated with the partially streamed content, or may involve the use of a controller located on the client to disable content streamed to the client.

Abstract: A method comprises associating a plurality of locks with a data object accessed concurrently by a plurality of threads, where each lock corresponds to a respective partition of the object. The method includes using a first non-blocking transaction (such as a Hardware Transactional-Memory (HTM) transaction) to attempt to complete a programmer-specified transaction. The first non-blocking transaction may access one or more of the locks but may not actually acquire any of the locks. In response to an indication that the first non-blocking transaction failed to complete, the method may include acquiring a set of locks in another non-blocking transaction, where the set of locks corresponds to a set of partitions expected to be accessed in the programmer-specified transaction. If the set of locks is acquired, the method may include performing the memory access operations of the programmer-specified transaction, and releasing the set of locks.

Abstract: A computer system may be configured to dynamically select a memory virtualization and corresponding virtual-to-physical address translation technique during execution of an application and to dynamically employ the selected technique in place of a current technique without re-initializing the application. The computer system may be configured to determine that a current address translation technique incurs a high overhead for the application's current workload and may be configured to select a different technique dependent on various performance criteria and/or a user policy. Dynamically employing the selected technique may include reorganizing a memory, reorganizing a translation table, allocating a different block of memory to the application, changing a page or segment size, or moving to or from a page-based, segment-based, or function-based address translation technique.

Abstract: A method and system for identifying multi-block indirect memory access chains. A method may include identifying basic blocks between an entry point and an exit point of a procedure, where the procedure includes a control statement governing its execution. It may be determined whether a probability of execution of a given basic block relative to the control statement equals or exceeds a first threshold value. If so, a respective set of one or more chains of indirect memory accesses may be generated, where each chain includes at least a respective head memory access that does not depend for its memory address computation on another memory access within the given basic block. Chains may be joined across basic blocks dependent upon whether the relative execution probabilities of the blocks exceed a threshold value.

Abstract: Prefetch information is generated for multi-block indirect memory access chains. A method may include selecting a chain of indirect memory accesses of a procedure, the chain comprising a head access that does not depend for its address on another prefetch candidate memory access within the procedure and an indirect access that depends for its address on the head access. The method may further include determining a prefetch-ahead value for the chain, and generating a load operation corresponding to the head access that specifies a target memory address that is dependent upon the prefetch-ahead value and an address of the head access. The method may further include, for a terminal indirect access of the chain, generating a respective prefetch operation that is dependent for its address computation on results of preceding load operations in the same manner as its corresponding terminal indirect access depends upon preceding accesses in the chain.

Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.

Abstract: The use of a token-based memory protection technique may provide memory protection in a computer system employing memory virtualization. A token-based memory protection technique may include assigning a unique identifier to an application, process, or thread, and associating the identifier with a block of memory allocated to that application, process, or thread. Subsequent to assigning the identifier, a packet requesting access to that block of memory may include a token to be compared to the identifier. A memory controller may be configured to associate the identifier with the block of memory and to compare the token in the memory request packet to the identifier before granting access. If a second block of memory is subsequently allocated to the application, process, or thread, the identifier may be disassociated with the first block of memory and associated with the second block of memory.

Abstract: An antenna module and a wireless communication device using the same are provided. The antenna module is used for receiving or transmitting at least a wireless signal. The antenna module includes three independent antennas each having a bottom end and a center line. The bottom ends are substantially disposed on the same plane. The bottom ends are substantially arranged in the shape of a regular triangle. Each distance between two neighboring bottom ends is larger than a quarter of the wavelength of the wireless signal. The included angle between each of the center lines and the plane substantially ranges from 50° to 80°.

Abstract: A computer system may employ a first memory virtualization and corresponding virtual-to-physical address translation technique for a first application executing on a processor and a second memory virtualization and corresponding virtual-to-physical address translation technique for a second application executing on the same processor transparent to the first application. Different virtualization and corresponding translation techniques may be employed on a per-thread basis, rather than a per-application basis. Different virtualization and corresponding translation techniques may be employed for accesses to different ranges of virtual or corresponding physical addresses. Different virtualization and corresponding translation techniques may employ different page sizes. A first or second virtualization and corresponding translation technique may include page-based, segment-based, or function-based virtual-to-physical address translation.

Abstract: A computer system employing memory virtualization may employ a function-based technique for virtual-to-physical address translation. A function-based translation technique may involve replacing a generic trap handler and one or more translation table look-ups with a function to compute a corresponding physical address from a given virtual address. The computer system may be configured to determine a translation function dependent on mappings in one or more translation tables. The computer system may be configured to reorganize a memory, to reorganize one or more translation tables, or to allocate different blocks of memory to an application prior to determining a translation function. Different applications or threads executing on the computer system may employ different translation functions. Different regions of memory may be accessed using different translation functions. Some virtual addresses may be translated using a function while others may be translated using one or more translation table look-ups.