Abstract: A method for modeling a system configuration, including isotonizing an unconstrained additive model of a cache architecture to obtain an isotonic additive model for the cache architecture, wherein the isotonic additive model is of the same functional form as the unconstrained additive model, smoothing the isotonic additive model using a flat spot technique to obtain a characterization of the cache architecture, and modeling a system configuration using the characterization of the cache architecture.

Abstract: A sampling mechanism is disclosed in which software can specify a property or properties which characterize samples of interest. For example, if the software is interested in cache behavior, the software can specify that information for memory operations, or only information for memory instructions which miss in one or more caches, be reported. The sampling mechanism may specify many such properties and events (properties and events may vary from processor to processor, and may also depend on which properties or events are considered useful for performance analysis).

Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of memory interconnects. In an embodiment of the present invention, a method of testing a memory interconnect between an external memory module and a chip is disclosed. The method includes: providing an on-chip memory controller coupled to the external memory module, the on-chip memory controller sending and receiving data to and from the external memory module; providing an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, the BIST module including an instruction register to store a plurality of instructions; testing the external memory module; and once the external memory module has successfully passed the testing, utilizing the external memory module in testing the memory interconnect.

Abstract: An exemplary CAD design flow modifies an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair from bottom up to locate and correct isolated via rule violations by adding metal features and vias in a respective patch cell associated with each cluster cell. A large complex design is thus divided into cells so that multiple processes can work concurrently as if every process were working on the top level of the design layout.

Abstract: In a garbage collector that more efficiently places newly promoted objects into a generation managed by the train algorithm, a promotion train is established near the oldest train and the objects are placed therein. If some objects are referenced from existing trains in the generation those objects are placed into those trains, and if any such objects are referenced from several existing trains, the objects are placed at the end of the youngest referencing train. The promotion train may be a new train that is placed, or a existing train that is selected, between the oldest train and the youngest train at a position based on the amount of memory compared to the size of a collection set. In the case of multiple collector threads, multiple cars in a promotion train or multiple promotion trains may be formed.

Abstract: Each driver has a global driver section comprising drive program code and global driver data, both defining driver operations associated with a corresponding class of devices. Each device has an associated driver instantiation comprising local driver data, having an internal pointer to the global driver section of the instantiated driver, and possibly at least one external pointer to another driver instantiation. A device registry forms a list of device registry entries, each corresponding to a respective one of the drive instantiations. Driveer client code may perform operations on a given device by fetching in the device registry a pointer to the driver instantiation associated with the given device, and then use operations provided by the associated driver instantiation, directly or using further operations reached in other driver instantiations by using iteratively the external printer.

Abstract: Improved techniques for loading class files into virtual computing machines are disclosed. The techniques seek to provide a mechanism that will generally improve the efficiency of virtual machines by selectively loading information into a virtual machine. A new class attribute (“load-attribute”) is defined and implemented for class files. This can be, for example, implemented as a “load-attribute” table that lists the components that have been selected for loading into the virtual machine. In addition, the load-attribute may provide references to the selected components in the class file. Accordingly, various components of the class file can be marked for loading and selectively loaded.

Abstract: A method and system are provided for defining a Web application including a graphical user interface and a functional component. A custom tag library is accessed, wherein the custom tag library includes one or more tags facilitating the use of XPath in JavaServer Pages (JSPs). A JSP representing the graphical user interface is defined. One or more tags is included in the JSP definition to enable interaction between the user interface and the functional component.

Abstract: A directory server including a supplier server, a consumer server in communication with the supplier server, a plurality of pluggable services that manage replication of data contained within the directory server from the supplier server to the consumer server, and a change sequence number used to determine ordering of operations performed on the consumer server. Replication of data is managed using the change sequence number.

Abstract: A method and apparatus are provided for determining a suitable inter-packet gap (IPG), or a suitable extension to be added to a default IPG as a packet is processed. The apparatus includes an adder to add an incremental measure of a packet to an existing measure and produce a new measure (e.g., in bytes). The apparatus further includes a comparator which, if the new measure exceeds a programmable threshold (e.g., a stretch ratio), issues a signal to increase the IPG and decreases the new measure by the threshold. The current measure is then stored (e.g., in a register) for addition to the next incremental measure. A counter tracks the number of signals received before the end of the packet, at which time the total is forwarded to a component configured to insert or apply the IPG and the counter is reset for the next packet.

Abstract: A method for printing documents containing transparent graphics objects includes creating a transparency list containing the transparent graphics objects of said document, and printing only objects contained in said transparency list as bitmaps.

Abstract: A computer system compnses a processor (2), memory (4) and a plurality of devices (6, 8, 12), the processor (2) and the memory (4) being operable to effect the operation of a fault response processor (AFR), and a device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for each of the devices. The fault response processor (AFR) is operable to generate a model which represents the processor (2), the memory (4) and the devices (6, 8, 12) of the computer system and the inter-connection of the processor (2), memory (4) and the devices (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL). The device driver (GRAPHICS, NETWORK, H2IO, IO2L, SERIAL) for each of the devices (6, 8, 12) is arranged, consequent upon a change of operational status of the device, to generate fault report data indicating whether the change of status was caused internally within the device or externally by another connected device. The devices of the computer system may be formed as a plurality of Field Replaceable Units (FRU).

Abstract: A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namespace or memory space or to see that a requested action is authorized for an object to be operated upon. Each program or set of programs runs in a separate context. Access from one program to another program across the context barrier can be achieved under controlled circumstances by using shared interface objects. Shared interface objects have a property that permits them to be accessed across the context barrier regardless of security restrictions that would otherwise apply. Shared interface objects, however, may enforce their own security rules independently of the context barrier.

Abstract: A method and apparatus are disclosed for testing the accuracy of digital test images generated by a computer graphics program executed on a computer graphics system. A test program is utilized to compare a test image with a reference image. Regional image quantification verification aims at an image comparison test that accepts minor color value differences and spatial shifts in rendered pixel values. The test image and reference image are divided into corresponding sub-regions. The average color value for each sub-region of the test image is compared to the average color value of the corresponding reference image sub-region and also to other nearby reference image sub-regions. A test image is unacceptably different from a reference image, if for any sub-region of the test image, no reference image sub-region is found with an average color value difference and spatial shift less than specified maximums.

Abstract: Disclosed are novel methods and apparatus for delta transfers in distributed file systems. In an embodiment, a communication system for transferring a delta of a file is disclosed. The communication system includes a sender site, a file transfer system, and a receiver site. The sender site includes a database with a trove section and a transfer section. The file transfer system includes a trove reader and a transfer reader. The trove reader may communicate with the trove and transfer sections. The transfer reader may have access to the transfer section. The receiver site receives the file delta from the transfer reader. The receiver site includes a file installer, which patches a previously installed version of the file with the file delta.

Abstract: Signed objects and sealed objects can be generated using embodiments of the invention. A signed object is an object that has an associated digital signature that can be used to authenticate the object. A sealed object is an object that is encrypted to limit access to only authorized entities. A signedObject class is used to create, maintain and authenticate a signed object. A sealed object is created, maintained, and authenticated using a sealedObject class. Nesting can be used to provide multiple levels of signing and/or sealing.

Abstract: A copying-type garbage collector operates in multiple concurrent threads. Each thread evacuates potentially reachable objects from the from space to the to space in a depth-first manner: if a thread has evacuated an object containing references to any from-space objects, it evacuates all of that object's descendants before it evacuates any other reachable objects. To keep track of descendants that must be evacuated before non-descendants can be, the thread places objects containing references to non-evacuated objects into a linked list maintained by pointers that it installs in the from-space locations from which the objects on the list were evacuated. Additionally, it divides the to space into local-allocation buffers (“LABs”) to which respective threads exclusively evacuate objects, and each thread maintains a LAB stack representing all the LABs it has filled that still contain references to unevacuated from-space objects.

Abstract: A method of determining an optimal transistor fanout. The method includes creating a sizing model by replacing at least one logic element in a circuit description with a sizing element that includes a dynamic resistor. The method also includes determining a steady state solution to the sizing model and determining at least one transistor fanout from the steady state solution.

Abstract: In one embodiment, a disk array storage system includes multiple disk drive modules that contain sets of drives and a number of storage controllers. Each storage controller is connected to a group of disk drives from two or more disk drive modules. The number of disk drives from the same disk drive module that are connected to the storage controller does not exceed a predefined number.