Abstract: A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.

Abstract: Methods and systems for data storage are described herein. In one aspect of the invention, an exemplary process includes receiving a first data being directed to a first storage volume, receiving a second data being directed to a second storage volume, writing the first data, as part of a first I/O (input/output) process which begins before a selected time, to a first storage image and a second storage image, the first storage image and the second storage image forming a data mirror prior to the selected time, wherein writes to one image are replicated to the other image, and writing the second data, as part of a second I/O process which begins after the selected time, to the second storage image but not to the first storage image, the second I/O process being capable of running while the first process runs. Other methods and apparatuses are also described.

Abstract: A serializer/deserializer pair with a discretionary loop-back mechanism is disclosed that enables a redundant high-bandwidth node architecture that benefits from the clever re-use of two identical integrated circuits. The first is an add/drop multiplexor and the second comprises the serializer/deserializer pair with discretionary loop-back. The illustrative embodiment comprises: a first serializer that serializes a first series of r-bit words to generate a first series of s-bit words; a first deserializer that deserializes a second series of s-bit words to generate a second series of r-bit words; and a multiplexor for selecting a third series of r-bit words from the first series of r-bit words and the second series of r-bit words; wherein r and s are both positive integers and r?s.

Abstract: One embodiment of the present invention provides a system that facilitates automated software installation on a remote computer over the Internet. The system operates by first initializing the remote computer with a custom operating system, which allows access to the remote computer over the Internet. Next, the system provides an archive locator to the remote computer, wherein the archive locator is a uniform resource locator (URL) or a proprietary resource locator. The system then requests an archive from the site specified by the archive locator. This archive includes an operating system and desired software packages pre-configured for the remote computer. The system downloads this archive to the remote computer and re-initializes the remote computer with the operating system and software packages in the archive.

Abstract: A system and method for stationary semantic zooming. Stationary semantic zooming allows selected non-spatial rendering attributes, such as level of detail, to be varied according to other specified non-spatial rendering attributes. Stationary semantic zooming allows low importance objects to be rendered with a lower level of detail than higher importance objects. A system and method for displaying network status and realty information using stationary semantic zooming are also disclosed.

Abstract: Web services interface policy constraints may be specified in a policy constraints language and policy processing, such as generating an intersection policy of two policies may be automated by a policy-processing engine. A policy constraint may be a specification of a value, range of values, or set of values that a particular requirement or offering is allowed to have. Hierarchies of requirements and/or offerings may also be expressed and matched such that a more specific case of a requirement or offering may be matched against a more general case of the same requirement or offering. Also, preferences among vocabulary items, vocabulary item values, policy constraints, and other elements of a policy may be specified and automatically determined by a policy-processing engine. Automated matching of consumer requirements against provider offerings may allow a policy-processing engine to process policies with specifications of requirements or offerings from any domain-specific schema.

Abstract: In one of the many embodiments of the present inventions, a system is provided which includes at least one server to execute at least one session where the at least one session includes data associated with a user. The system also includes at least one stateless client coupled to the at least one server where the at least one stateless client obtains the at least one session from the at least one server.

Abstract: A tool for automatically generating a reduced size circuit model including inductive interaction properties is provided. Such inclusion of inductive properties in the reduced size circuit model allows for a more complete and accurate circuit model than those created by conventional methods. Further, a technique for automatically generating a reduced size circuit model including inductive properties that uses less memory space and operates faster than conventional methods is provided.

Abstract: Prediction of a clock skew for an incomplete integrated circuit design, includes (a) selecting a first metal layer having at least one clock design figure, (b) placing, for a minimum clock skew prediction, clock source locations on the clock design figure in accordance with a first predetermined minimum distance between adjacent clock source locations, (c) placing, for a maximum clock skew prediction, a clock source location on a largest clock design figure in the first layer, such that the clock source location has a largest distance from a via to a lower layer, and (d) placing, for an intermediate clock skew prediction, clock source locations on intersections between the clock design figure and a virtual clock grid created for the first metal layer, the virtual clock grid having a predetermined offset from a design boundary and a predetermined pitch between grid lines.

Abstract: Provided are a method, system, program, and data structure for implementing a locking mechanism to control access to a shared resource. A request is received to access the shared resource. A determination is made of whether a first file has a first name. The first file is renamed to a second name if the first file has the first name. A second file is updated to indicate the received request in a queue of requests to the shared resource if the first file is renamed to the second name. An ordering of the requests in the queue is used to determine whether access to the shared resource is granted to the request. The first file is renamed to the first name after the second file is updated.

Abstract: A digital delay locked loop uses a delay array to delay an input signal by an amount indicated by a delay code. A phase of the resulting delayed signal is compared to a corresponding phase of the input signal, and dependent on the comparison, the delay code is updated to indicate whether the delay array needs to provide more delay or less delay. The digital delay locked loop also uses a detection circuit that monitors for a predetermined condition of the delay code. In response to detection of the predetermined condition, the delay code is automatically reset to a value different than a value of the delay code present at a previous reset or initial startup of the digital delay locked loop.

Abstract: A filtering engine may read samples from a sample buffer and spatially filter (e.g., convolve) the samples to generate pixels. The pixels may have a high dynamic range of luminance. Thus, the filtering engine may apply automatic gain control and/or dynamic range compression on pixel luminance or pixel color. A rendering engine may generate the samples in response to received graphics data and store the samples in the sample buffer. A sample may include one or more data fields which represent color (or intensity) information. The data field may include exponent information (e.g., an amplification control bit) and a mantissa. The exponent information may determine an extent to which the mantissa is amplified (e.g., left shifted) in the filtering engine.

Abstract: A graphics system comprises a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor generates samples in response to received stream of graphics data. The sample buffer may be configured to store the samples. The sample-to-pixel calculation unit is programmable to generate a plurality of output pixels by filtering the rendered samples using a filter. A filter having negative lobes may be used. The graphics system computes a negativity value for a first frame. The negativity value measures an amount of pixel negativity in the first frame. In response to the negativity value being above a certain threshold, the graphics systems adjusts the filter function and/or filter support in order to reduce the negativity value for subsequent frames.

Abstract: Methods and systems for accessing information in and loading encrypted information to memory. A processor provides virtual address information to a memory management unit. In response, the memory management unit retrieves a key tag and physical address information corresponding to the virtual address information. The memory management unit then sends the key tag and physical address information to the processor. The processor then determines whether a memory location corresponding to the physical address information is encrypted based on the key tag, and retrieves a secret key using the key tag based on the determining. Thereafter, information read from the memory location is decrypted using the secret key.

Abstract: Provided are a method, system, and program for making resources available for access to a client. A list is provided indicating a plurality of resources to make available for access to clients over a network and the list is processed to determine resources. Attributes of the resources are determined and reference codes are generated for the determined resources based on the determined attributes. The reference codes are associated with the resources for which the codes were generated. In response to receiving a request to one reference code from the client, a determination is made from the resource associated with the requested reference code and returning the determined resource to the requesting client.

Abstract: A circuit and method for boosting bitline performance uses a bitline booster circuit to allow long bitlines, with large numbers of memory cells attached, to discharge to a digital zero in a faster time. One bitline booster circuit requires only two additional NOR gates, two additional transistors, and one additional control signal. Consequently, the bitline booster circuit does not require a significant number of added components, does not require multiple control signals and takes up minimal additional silicon area.

Abstract: An apparatus for controlling removal of a component from a chassis may include an engaging member and a control member. The engaging member may engage a portion of the chassis when the component is withdrawn to a predetermined position in the chassis to inhibit removal of the component from the chassis. The control member may be operated to disengage the component from the chassis such that the user can remove the component from the chassis. The control member may be a handle that disengages the engaging member from the chassis when the handle is deployed.

Abstract: An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

Abstract: Management of lightweight directory access protocol (LDAP) service may be accomplished through the use of remote mirroring and a unique application program interface (API). Both a primary and a secondary LDAP server are maintained. Any modification to the primary LDAP server is then mirrored on the secondary LDAP server. When a call is attempted on the primary server, if it fails, the call is retried on the secondary LDAP server. The API allows for specialized grammar for commands that permits the system to handle primary (and secondary) LDAP server failure.

Abstract: A graphical processing system comprising a computational unit and a shadow processing unit coupled to the computational unit through a communication bus. The computational unit is configured to transfer coordinates C1 of a point P with respect to a first space to the shadow processing unit. In response to receiving the coordinates C1, the shadow processing unit is configured to: (a) transform the coordinate C1 to determine map coordinates s and t and a depth value Dp for the point P, (b) access a neighborhood of depth values from a memory using the map coordinates s and t, (c) compare the depth value DP to the depth values of the neighborhood, (d) filter binary results of the comparisons to determine a shadow fraction, and (e) transfer the shadow fraction to the computational unit through the communication bus.