Abstract: A method and system perform a rounding step of a floating point computation on at least one floating point operand to preserve an inexact status. Inexact status information generated from the rounding step may be encoded within the result, instead of requiring a separate floating point status register for the inexact status information. In one embodiment, inexact status information is preserved by determining whether the at least one operand is inexact. Further, an intermediate result of the floating point computation is analyzed to determine whether it is inexact. Finally, the intermediate result is rounded based on whether the at least one operand is inexact and whether the intermediate result is inexact to preserve an inexact status of the at least one operand and the intermediate result.

Abstract: In one general aspect, a stream-based memory circuit is disclosed that includes physical storage elements and at least a first physical access port. A stream-based access controller is operatively connected to the physical storage elements and to the access port. The controller includes function-specific hardware logic operative to access data as streams in the physical memory in response to stream-based access commands at the access port.

Abstract: Versioning may be utilized in a knowledge base decision tree in order to provide several useful features. To accomplish this, when a decision tree is traversed, the decision tree representing a knowledge base and having non-leaf nodes with one or more branches representing possible symptoms, and leaf nodes with no branches, branches may be followed corresponding to symptoms experience by the application until a leaf node is reached. This traversal may be recorded as a version, with subsequent traversals having a different version. This allows a user to rerun performance tuning either from the beginning or from an earlier node without having to re-enter information already provided. It also allows a user to resume the performance tuning should he be interrupted in the middle, such as by a crash or by having to halt a long traversal.

Abstract: One embodiment of the present invention provides a system that facilitates instant failover during packet routing by employing a flooding protocol to send packets between a source and a destination. Upon receiving a packet containing data at an intermediate node located between the source and the destination, the system determines whether the packet has been seen before at the intermediate node. If not, the system forwards the packet to neighboring nodes of the intermediate node. In one embodiment of the present invention, forwarding the packet to neighboring needs involves forwarding the packet to all neighboring nodes except the node from which the packet was received. In one embodiment of the present invention, determining whether the packet has been seen before involves examining a sequence number, SR, contained within the packet to determine whether the sequence number has been seen before.

Abstract: A method to convert a wire layout geometry to a filament topology for determination of chip resistance is provided. The method includes resolving overlap of layout segments of the wire layout geometry and inserting a vertical filament into each of the layout segments. The method further includes connecting vertical filaments using lateral connections and merging connected parallel filaments. The method also includes removing open filaments and modifying the filament structure in a bend region based on relative dimensions of the vertical filaments within the bend region.

Abstract: An apparatus and method for scheduling execution of multiple threads on a shared processor resource is described in connection with a multithreaded multiprocessor chip. Using a thread selection policy that switches between available threads every cycle to give priority to the least recently executed or scheduled threads, different threads are able to operate in a way that ensures no deadlocks or livelocks while maximizing aggregate performance and fairness between threads. Prioritization is accomplished by monitoring and sorting thread status information for each thread, including speculative states in which a thread may be speculatively scheduled, thereby improving usage of the execution pipeline by switching a thread in with a lower priority.

Abstract: A processor chip is provided. The processor chip includes a plurality of processing cores where each of the processing cores being multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes a centrally located arbiter configured to sort multiple requests received from the plurality of processing cores and the crossbar is defined over the plurality of processing cores. In another embodiment, the processor chip is oriented so that the cache bank memories are defined in the center region. A server is also included.

Abstract: A multi-thread processor including a processing core. The processing core including multiple threads and a scheduler. The scheduler includes a thread state register. The thread state register being capable of storing a selective wait state for a selected one of the threads. A method of scheduling threads in a multi-thread processor is also disclosed.

Abstract: An enhanced Java Bytecode verifier suitable for operation in a Java computing environment is disclosed. The enhanced Java Bytecode verifier operates to determine whether one or more Java conventional Bytecode commands within a stream of Bytecodes are likely to place a reference to a Java object on the execution stack. In one embodiment, the conventional Java Bytecode commands identified as such are translated by the enhanced Java Bytecode verifier into one or more corresponding Java commands. When a corresponding command is executed, the reference associated with the conventional Java command is placed on a reference stack as well as the execution stack.

Abstract: The invention describes a method an apparatus to minimize the costs introduced in the native code of a method M in order to make it executable (concurrently or serially) by multiple tasks, wherein M's native code is produced by the dynamic compiler of a multitasking virtual machine. One embodiment of the present invention describes a mechanism that annotates the shared runtime representation of classes with information that identifies the particular event that triggered the initialization of these classes, and in particular, if that event is the execution of class initialization barrier from a method of another class. These annotations are then used during each dynamic compilation of a method M of a class C to determine when native code corresponding to a class initialization barrier needs to be generated in the task re-entrant native code produced by the dynamic compiler for M.

Abstract: One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.

Abstract: A method generates and verifies a design-for-test (DFT) library for an automatic test pattern generator (ATPG) tool. The method includes (a) creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool, (b) creating a register transfer level (RTL) description for each module, (c) performing synthesis using the synthesis library and the RTL description to create a gate level description for each module, and (d) generating the DFT library by converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool to create a DFT file for each module. The method may further include (e) converting the DFT files into a RTL description to create a pseudo-RTL description for each module, and (f) comparing the RTL description and the pseudo-RTL description for verification of the DFT library.

Abstract: Various embodiments of message gate pairs are described. A message gate pair may provide a mechanism for communicating requests from clients to services and response from services to clients. A message gate pair may be used to create a secure atomic bi-directional message channel for request-response message passing. The distributed computing environment may employ a message transport in which a message gate exists on both the client and the service. The two gates may work together to provide a secure and reliable message channel. Client and service gates may perform the actual sending and receiving of the messages from the client to the service using a protocol specified in a service advertisement. The message gates may provide a level of abstraction between a client and a service. A client may reference a service through a message gate instead of referencing the service directly.

Abstract: Embodiments of a system and method for hierarchically organizing rules and for evaluating and executing the hierarchy of rules. Each rule in the hierarchy of rules may include a precondition and an action to be executed if the precondition is met. When evaluating and executing the rules, if a precondition of a rule in the hierarchy is not met, then the action of the rule is not executed. Further, rules that descend from the rule in the hierarchy of rules are precluded from evaluation and execution. In one embodiment, modification of the hierarchy of rules may be performed without modification to an application using the hierarchy of rules.

Abstract: A technique for handling a condition code modifying instruction in an out-of-order multi-stranded processor involves providing a condition code architectural register file for each strand, providing a condition code working register file, and assigning condition code architectural register file identification information (CARF_ID) and condition code working register file identification information (CWRF_ID) to the condition code modifying instruction. CARF_ID is used to index a location in a condition code rename table to which the CWRF_ID is stored. Thereafter, upon an exception-free execution of the condition code modifying instruction, a result of the execution is copied from the condition code working register file to the condition code architectural register file dependent on CARF_ID, CWRF_ID, register type information, and strand identification information.

Abstract: A computer system includes a register that is configured to contain a zero value. In response to a predetermined occurrence on the computer system, such as a hardware interrupt, the computer system launches a trap routine. This routine generates output data that needs to be stored within the memory space of the computer system. In order to write out this data from within the trap routine, a desired target address is specified as a negative offset from the zero value stored in the register. This avoids the need to have to locate another (unused) register in which to store the write address.

Abstract: Disclosed are novel methods and apparatus for manipulating and generating a real-time counter in network computing environments. In an embodiment, a method of tracking a defect is disclosed. The method includes providing a defect abstract, the defect abstract including information to identify the defect; identifying a component having the defect; assigning a user to resolve the defect; and assigning a defect number to identify the defect, the defect number obtained by incrementing a counter value stored in a file, the file being accessible by a single user at a time.

Abstract: Virtual registers are mapped to architectural or physical registers according to a register map that is configurable with software. In one embodiment, only privileged software can configure the register map. In another embodiment, a portion of the register map is configurable with non-privileged software, and another portion is only configurable with privileged software. In yet another embodiment the register map is fully configurable by user software. The configurable register map provides backwards compatibility to code written for hardware-defined register mapping, while allowing flexible approaches to register mapping in code generated for a processor architecture using a software controllable register map.

Abstract: A server blade is provided with an enclosure. The server blade can be provided with a plurality of processors in the enclosure. The server blade can be configured as a field replaceable unit removably receivable in a carrier of a modular computer system, for example a high density blade server system. The enclosure for such a multiprocessor server blade can be larger that a standard enclosure for a single processor server blade. The carrier can be configured to receive such an oversized server blade enclosure as well as a standard enclosure.

Abstract: A smaller footprint is loaded into the virtual machine by loading only those methods of library classes that the executed application actually requires. This is accomplished by taking the classes of the targeted application and statically determining which methods of these classes, as well as of the library classes, can actually be used by the application. A generated method usage map of usable methods for each class are saved in a file. At runtime, the virtual machine consults this file and selectively loads into memory only those classes listed in the file. This saves memory space in the virtual machine and speeds execution.