Abstract: The excitation of processing paths in a microelectronic circuit is organized by providing one or more pieces of input information to a decision-making software, and executing the decision-making software to decide, whether one or more of said processing paths of the microelectronic circuit are to be excited with test signals. Deciding that said processing paths are to be excited with said test signals results in proceeding to excite said one or more of said processing paths with said test signals and monitoring whether timing events occur on such one or more excited processing paths. A timing event is a change in a digital value at an input of a respective register circuit on an excited processing path, which change took place later than an allowable time limit defined by a triggering signal to said respective register circuit.

Abstract: A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path.

Abstract: The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value.

Abstract: The performance of an adaptive microelectronic circuit is at least partly configurable by selecting a value of an operating parameter. On processing paths, data inputs of register units are coupled to outputs of respective logic units for temporarily storing output values of said logic units. A plurality of timing event monitors respond to a digital value at a data input of a monitored register unit changing later than an allowable time limit by generating a timing event observation signal. The plurality of timing event monitors form a plurality of monitor groups, each monitor group being coupled to a branch of a triggering signal tree for coupling a monitor-group-specific triggering signal to the monitor group independently of other monitor groups. A control unit selectively allows or disables the propagation of the respective triggering signals into said branches of the triggering signal tree.

Abstract: A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.

Abstract: Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal.

Abstract: A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

Abstract: Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units.

Abstract: A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element.

Abstract: A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

Abstract: Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units.

Abstract: A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path.

Abstract: It is an objective to provide timing event detection. According to a first aspect, a device, comprises: a clocked conditional buffer configured to set an output of the clocked conditional buffer to a first state during a non-detection period; the clocked conditional buffer further configured to toggle the output from the first state to the second state during a detection period, wherein the toggling being enabled by either one of the two states; and the clocked conditional buffer further configured to guarantee that the output is toggling only to one direction during the detection period. This may prevent false event detections. Furthermore, with respect to a timing point of view, one is able to operate without pulses, where pulse width may be difficult to manage in low voltages.

Abstract: A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

Abstract: Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal.

Abstract: A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element.

Abstract: A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

Abstract: A level shifter comprises a first control switch (207) for connecting an output terminal to a first supply voltage (VDDH) to set an output signal to be high, and a second control switch (208) for connecting the output terminal to a signal ground (GND) to set the output signal to be low. The level shifter comprises a pre-charging switch (210) for connecting the output terminal to the first supply voltage, and an input gate circuit (211) for controlling an ability of an input signal to control the second control switch. The level shifter comprises a keeper circuit (212) for controlling the first control switch based on the output signal. The first control switch is controlled with the first supply voltage when the output signal is low, and with a second supply voltage that is between the first supply voltage and the signal ground when the output signal is high.