Patents Assigned to MIPS Technology, Inc.
  • Patent number: 8171262
    Abstract: A method and apparatus for overlaying hazard clearing with a jump instruction within a pipeline microprocessor is described. The apparatus includes hazard logic to detect when a jump instruction specifies that hazards are to be cleared as part of a jump operation. If hazards are to be cleared, the hazard logic disables branch prediction for the jump instruction, thereby causing the jump instruction to proceed down the pipeline until it is finally resolved, and flushing the pipeline behind the jump instruction. Disabling of branch prediction for the jump instruction effectively clears all execution and/or instruction hazards that preceded the jump instruction. Alternatively, hazard logic causes issue control logic to stall the jump instruction for n-cycles until all hazards are cleared. State tracking logic may be provided to determine whether any instructions are executing in the pipeline that create hazards. If so, hazard logic performs normally.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: May 1, 2012
    Assignee: MIPS Technology, Inc.
    Inventors: Niels Gram Jeppesen, G. Michael Uhler
  • Patent number: 7509480
    Abstract: An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program. The apparatus allows the multiple-ISA CPU to select a particular ISA decoding mode corresponding to a program instruction. The program instruction is located at an address within an address space of the multiple-ISA CPU. The apparatus includes a plurality of boundary address registers and ISA mode selection logic. The plurality of boundary address registers can be dynamically loaded to partition the address space into a plurality of address ranges, where each of the plurality of address ranges corresponds to each of a plurality of ISA decoding modes. The ISA mode selection logic is coupled to the plurality of boundary address registers.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: March 24, 2009
    Assignee: Mips Technology, Inc.
    Inventors: Michael Gottlieb Jensen, Morten Stribaek
  • Patent number: 7386701
    Abstract: A processor capable of executing prefetching instructions containing hint fields is provided. The hint fields contain a first portion which enables the selection of a destination indicator for refill operations, and a second portion which identifies a destination.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: June 10, 2008
    Assignee: MIPS Technology, Inc.
    Inventor: Todd C. Mowry