Abstract: A method of sharing a plurality of registers in a shared register pool among a plurality of microprocessor threads begins with a determination that a first instruction to be executed by a microprocessor in a first microprocessor thread requires a first logical register. Next a determination is made that a second instruction to be executed by the microprocessor in a second microprocessor thread requires a second logical register. A first physical register in the shared register pool is allocated to the first microprocessor thread for execution of the first instruction and the first logical register is mapped to the first physical register. A second physical register in the shared register pool is allocated to the second microprocessor thread for execution of the second instruction. Finally, the second logical register is mapped to the second physical register.

Abstract: A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.

Abstract: A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output.

Abstract: A method of tracing processor instructions includes forming a compressed trace stream with a dynamic unit width indicator and a value block. The dynamic unit width indicator includes an address/data width indicator qualified by a unit indicator. The unit value block has a width that is a function of the address/data width indicator and the unit indicator.

Abstract: A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented.

Abstract: A computer has a memory adapted to store a first plurality of instructions encoded with a first vector size and a second plurality of instructions encoded with a second vector size. An execution unit executes the first plurality of instructions and the second plurality of instructions by processing vector units in a uniform manner regardless of vector size.

Abstract: A computer includes a memory and a processor connected to the memory. The processor includes memory segment configuration registers to store defined memory address segments and defined memory address segment attributes such that the processor operates in accordance with the defined memory address segments and defined memory address segment attributes to allow kernel mode access to user space virtual addresses for enhanced kernel mode memory capacity.

Abstract: A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.

Abstract: A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.

Abstract: Embodiments provide systems and methods for controlling the use of processing algorithms, and applications thereof. In an embodiment, authorization to use an algorithm is validated in a system having a processor capable of executing user defined instructions, by executing a user defined instruction that writes a first value to a first storage of a user defined instruction block, uses the first value to transform a second value located in a second storage of the user defined instruction block, and compares the transformed second value to a third value located in a third storage. Use of the algorithm is permitted only if the comparison of the transformed second value to the third value indicates that use of the algorithm is authorized. In another embodiment, authorization to use an at least partially decrypted algorithm is validated via a key for enablement.

Abstract: A microprocessor includes one or more N-way caches and a way prediction logic that selectively enables and disables the cache ways so as to reduce the power consumption. The way prediction logic receives an address and predicts in which one of the cache ways the data associated with the address is likely to be stored. The way prediction logic causes an enabling signal to be supplied only to the way predicted to contain the requested data. The remaining (N?1) of the cache ways do not receive the enabling signal. The power consumed by the cache is thus significantly reduced.

Abstract: A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented.

Abstract: A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.

Abstract: The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined by a first clock signal and a second digital circuit that operates at a second rate determined by a second clock signal. The first digital circuit is coupled to the second digital circuit by a bus that is used for communications between the first digital circuit and the second digital circuit. A clock ratio controller is used to adjust the frequency of the first clock signal and/or the second clock signal in response to a power management signal without causing a loss of synchronization between the first digital circuit and the second digital circuit.

Abstract: A number of coherence domains are maintained among the multitude of processing cores disposed in a microprocessor. A cache coherency manager defines the coherency relationships such that coherence traffic flows only among the processing cores that are defined as having a coherency relationship. The data defining the coherency relationships between the processing cores is optionally stored in a programmable register. For each source of a coherent request, the processing core targets of the request are identified in the programmable register. In response to a coherent request, an intervention message is forwarded only to the cores that are defined to be in the same coherence domain as the requesting core. If a cache hit occurs in response to a coherent read request and the coherence state of the cache line resulting in the hit satisfies a condition, the requested data is made available to the requesting core from that cache line.

Abstract: A method of walking page tables includes comparing a virtual address to a plurality of virtual address bit segments to identify a match. Each virtual address bit segment is associated with a page table level that has a page table base address. A designated page table base address is received in response to the match. The page table walk starts at the designated page table, thereby skipping over earlier page tables.

Abstract: A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.

Abstract: A method includes storing defined memory address segments and defined memory address segment attributes for a processor. The processor is operated in accordance with the defined memory address segments and defined memory address segment attributes.

Abstract: A microprocessor includes an N-way cache and a logic block that selectively enables and disables the N-way cache for at least one clock cycle if a first register load instructions and a second register load instruction, following the first register load instruction, are detected as pointing to the same index line in which the requested data is stored. The logic block further provides a disabling signal to the N-way cache for at least one clock cycle if the first and second instructions are detected as pointing to the same cache way.

Abstract: A method of fetching data from a cache begins by preparing to fetch a first set of cache ways for a first data word of a first cache line a using a first thread. Next, in parallel, a second set cache ways for a first data word of a second cache line is prepared to be fetched using a second thread, and data associated with each cache way of the first set of cache ways are fetched using the first thread. Also performed in parallel, data associated with each cache way of the second set of cache ways is fetched using the second thread and a third set of cache ways for a second data word of the first cache line is prepared to be fetched using the first thread based on a selected cache way, the selected cache way selected from the first set of cache ways.