Abstract: In a non contact IC card for generating a power supply voltage from electric waves transmitted via wireless communication from a base unit, a reset signal generating circuit is provided to reset the internal circuits when the power supply voltage rises to a predetermined operating voltage and when it is lowered below a minimum voltage of voltages which ensure the normal operation of the internal circuits, thereby operations such as a writing operation in the internal circuits can be made stable and the time required for communication can be shortened.

Abstract: A serial input/output circuit with an automatic transfer function can easily re-transfer correct data even if a transfer error occurs during automatic transfer. When the transfer of one data has been completed, an automatic transfer data pointer normally automatically updates its contents and indicates an address in an automatic transfer RAM, which corresponds to data to be next transferred. An error generation active circuit makes an error control signal significant when an error detecting circuit detects an error produced in data or the occurrence of the error in the data is notified from a transfer opposite party. When the error control signal is made significant, the automatic transfer data pointer and the transfer counter do not update their values.

Abstract: A reader/writer includes an input/output unit for inputting and outputting bidirectional signals from and to an external host computer, a transmitter/receiver for transmitting to and receiving from a noncontact IC card bidirectional electromagnetic-wave signals, the controller being electrically connected to the input/output unit and transmitter/receiver for transferring signals between them. The reader/writer thus assists in transferring signals between an external host computer and a noncontact IC card. The operation of the reader/writer is so simple that communication between a noncontact IC card and an external host computer can be achieved efficiently. The software implemented in the reader/writer need not be modified but can still cope with various application programs running in the noncontact IC card and external host computer.

Abstract: In a timer device, the counter thereof counts the number of the pulses of a pulse signal input from an external apparatus up to a count initial value to output a count ending signal at the time of the end of the counting, and the control signal generator thereof generates a signal for controlling the external apparatus on the count ending signal output from the counter, and further the count operation controller thereof controls the count operation of the counter on a state change signal indicating the change of the state of the external apparatus. Thereby, the timer device can execute extensive processing by means of few counters.

Abstract: A microcomputer in which a voltage drop in a power source is detected by a voltage detecting circuit, and a capacitor is connected to a first power source and/or a second power source on the basis of a detection signal of said detecting circuit thereby to be charged/discharged, so that a reset signal is generated. The supply of a clock signal is controlled on the basis of said detection signal. When a source voltage of the microcomputer is found to be lower than a reference voltage but recovering in a short time, it is possible to resume a programmed operation from a temporary cut-off state without initializing the program.

Abstract: A non-contact type IC card includes a programmable memory divided into a user area for storing application data, and a system area for storing a system password and a system password effective code indicating requirement of collation of the system password. If the system area of the memory includes the system password effective code, access to the system area by an external apparatus is permitted only when passwords are identical as a result of password collation. If the system area does not include the system password effective code, the access by the external apparatus can be permitted without the password collation.

Abstract: A microprocessor comprises a control section for receiving a transfer instruction and transferring N-bits of M-bit data stored at a transfer-source address in a first memory to a transfer-destination address in a second memory in response to a received transfer instruction. In this microprocessor, the transfer of N-bits is performed with the execution of a single transfer instruction. Hence, the memory area required for storing the transfer instructions is reduced, and the residual memory area can be used for other purposes, which improves the efficiency in the use of the memory. The control section stores in the first memory of the microprocessor all the interim results obtained during the execution of a transfer instruction and outputs only the final result to the external memory, reducing the number of machine cycles required for data transfer between the microprocessor and the memory, and further reducing the execution time for data transfer in the microprocessor.

Abstract: A logic simulation device includes an indefinite value generating signal line extracting unit, a propagation deciding unit and a message output unit. The logic simulation device is supplied with circuit connection data of a logic circuit and input signal data employed for simulating the logic circuit. The indefinite value generating signal line extracting unit extracts a signal line which enters a floating state in excess of an allowance time or that causes a collision of logic states as an indefinite value generating signal line. The propagation deciding unit decides whether or not a propagation candidate gate having a propagation input end which is connected with an indefinite value generating signal line is in a state propagating the indefinite value to its output. The propagation deciding unit decides that the indefinite value generating signal line is an error signal line causing an error only when the propagation candidate gate is in a state of propagating the value at the propagation input end.

Abstract: In a switch level simulation system of the present invention, bidirectional switch models are allocated more accurately at locations which need to be bidirectional in circuit connection information and uni-directional switch models corresponding to the flow direction of a signal are allocated at the other locations. The connection information extracting section extracts the connection state of each device in a circuit indicated by circuit information and produces connection information. The input/output type determining section determines whether or not a switching device in a circuit is bidirectional and the flow direction of a signal in a uni-directional switching device, according to connection information. The circuit connection information generating section generates circuit connection information to be used by a simulation executing section, using the result of determining of the input/output type determining section.

Abstract: In a semiconductor circuit design verifying apparatus, a parasitic device retrieving part retrieves a parasitic device for a signal line connecting first stage active devices to a next stage active device. A time constant computing device computes a time constant between each first stage active device and the next stage active device including the parasitic device for the signal line between the first stage active devices and the next stage active device. An output data generating device outputs the time constant and information associated with the time constant to a user.

Abstract: In an IC card, a user area is set to have a first area in which a write password is made valid, and a second area in which a read password is made valid. When a write command for the first area is sent together with a password from a read/write apparatus, the password is collated with the write password. When a read command for the second area is sent together with a password, the password is collated with the read password. As a result of the collation, when the passwords are identical, the respective commands are executed.

Abstract: A microcomputer including an EEPROM in which data may be stored and from which stored data may be read either under control of a central processing unit of the microcomputer or under direct external control. The microcomputer includes separate inputs for data input and data output signals when storing and reading is under the control of the central processing unit and when storing and reading of data is under direct external control. The central processing unit may inhibit direct external control of storing data in and reading data from the EEPROM.

Abstract: An A/D converter wherein data obtained by A/D converting an analog signal in an A/D converting unit is stored in a first register, the data in the first register and the data in a second register are compared to each other by a comparator, and when the data in the first register is larger (or smaller) than that in the second register, a first switching means is closed so that the data in the first register is stored in the second register. In the second register, a maximum value (or a minimum value) of the A/D-converted data hitherto obtained is stored.

Abstract: An analog-to-digital converter includes a comparator for comparing a voltage output by a digital-to-analog converter with an input analog voltage at each bit of an n-bit word. The input analog voltage and the analog output voltage of the digital-to-analog converter are alternatingly used as the reference in the comparison, i.e., for every other bit of the n bits. A one-bit result-of-comparison signal indicative of the result of the comparison is output for each of the n bits. Only alternating result-of-comparison signals are inverted and the inverted and non-inverted result-of-comparison signals are stored in a successive approximation register as the converted digital signal and are supplied to the digital-to-analog converter for use in the comparison.

Abstract: A microcomputer comprising an exclusive register 61, an STP/WIT instruction valid/invalid control circuit 60 which detects that data are written consecutively in the register 61 and that values of the data are in a predetermined combination, and AND gates 11 and 12 which permit execution of the STP instruction and the WIT instruction for stopping clock .phi. only when the predetermined signal is outputted from the STP/WIT instruction valid/invalid control circuit 60, and capable of avoiding the instruction for stopping the internal clock being executed by mistake.

Abstract: The temperature of the circuit to be verified is evaluated. A simulation executing section (101) executes logic simulation of the circuit to be verified expressed in function block units at function block level. A circuit action extracting section (103) extracts an actin mode of a function block in its process. A total current consumption calculating section (105) calculates the total current consumption which is the current consumed in the entire circuit to be verified, on the basis of the data of current consumption in each action mode and extracted action mode. An average current calculating section (107) calculates the average current which is the average of the total current consumption over the check period, reflecting the thermal characteristic of the circuit to be verified. An allowable temperature judging section (109) calculates the temperature of the circuit to be verified according to this average current, and compares with an allowable current.

Abstract: A switching regulator is composed of digital circuits only. A switching regulator (30) comprises a driver (2) for directly controlling the operation of a switching transistor (1), and an OR gate (6) for determining the logic issued by the driver (2). An output terminal (Q) of an RS flip-flop (5) is connected to one input end of the OR gate (6), the output of a timer (40c) is applied to a set terminal (S) of the RS flip-flop (5), and the output of a comparator (4) is applied to a reset terminal (R1) through an OR gate (7). At a non-reverse input end of the comparator (4), a reference voltage (VE) is applied by a D/A convertor (40b), while a feedback voltage (VFB) is applied to a reverse input end. Accordingly, chopping of the switching transistor (1) is done on the basis of a rectangular pulse.

Abstract: A analog-to-digital converting device includes an analog-to-digital converting operation control unit for temporarily stopping an analog-to-digital converter in response to a trigger signal applied thereto and for restarting the analog-to-digital converter by imposing the operation conditions, which have been initially set up, on the analog-to-digital converter again. The device can forcefully terminate a scanning operation and restart analog-to-digital converting operations in a scan mode under the initially set up operating conditions without having to use an interrupt program executed by a CPU.

Abstract: A noncontacting IC card system occupying a relatively small area without requiring a provision for a dead zone or unnecessary communication area outside a gate. A transmitting antenna 11 is provided between two contiguous gates i.e., on the inner sides of the gates, and receiving antennas are provided respectively toward the sides opposite to the transmitting antenna of the gates i.e., on the outer sides of the gates. It is thereby not necessary to provide a dead zone between the gates and an unnecessary communication area does not occur outside the gate.

Abstract: A microcomputer has a timer register 10 for storing period data of a carrier, timer registers 4A and 4B for individually storing positive phase and negative phase time width data of a control signal which is synchronized with the carrier, and an operation unit 13 for subtracting the value of the positive phase time width data of the control signal from a value of the period data. The time width data obtained as a subtraction result is supplied to the timer register 4B. The load on the CPU when the revolution of an induction motor is controlled is reduced.