Abstract: A single-chip microprocessor with a self-testing function for quickly detecting internal errors or defects while mounted to a circuit board without adversely affecting any external electronic devices connected thereto.A single-chip microprocessor comprising a built-in self-testing function for testing the internal circuitry thereof comprises a test mode signal output means for outputting the test mode signal when in the test mode, which is a mode for self-diagnostic testing of the internal circuitry; and an external output holding means disposed to the external output means for outputting signals from an external output terminal, and holding the output signal status of the external output terminal while the test mode signal is input from the test mode signal output means; and testing the internal circuitry of the single-chip microprocessor while holding the output signal status of the external output terminal.

Abstract: An in-circuit emulator comprises a pod portion mounted with a microcomputer equivalent to a target microcomputer and an emulator main body which offers a debug function. There are provided between the pod portion and the emulator main body a common bus to be connected either to a bus of a controlling microcomputer in the emulator main body or to a bus of a microcomputer in the pod portion and a serial input-output line for realizing information exchange between the controlling microcomputer and the pod portion.

Abstract: A semiconductor memory device pre-charges the electric potential of a selected bit line up to a predetermined electric potential, and judges the electric potential of the selected bit line on the basis of the predetermined electric potential as a threshold value after the pre-charge. Thereby, a semiconductor memory device capable of being read out at high speed can be realized.

Abstract: A microcomputer or a one-chip computer has address pins and data pins provided separately, and when a specified control signal is provided, the address pins act as multiplex pins for address and data signals. Further, a combination of bits for address signals and bits for data signals to be provided to the multiplex pins are changed according to a width of an external bus. For example, the data bits D.sub.i are combined with the address bits A.sub.i, as used previously. Further, the data bits D.sub.i-1 are combined with the address bits A.sub.i by shifting by one bit with respect to the address bits. One of the two types of the combination can be selected. If the microcomputer has 16-bit address pins, it can be connected to 8-bit memories having independent address and data pins, while it can also be connected to 8-bit peripherals having multiplex pins without using an external circuit for separating address and data signals.

Abstract: Addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of a plurality of flash memory devices such that the addresses for the plurality of continuous logic blocks are respectively distributed into the plurality of flash memory devices. When block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two of the flash memory devices in which physical blocks to be erased exist, in such a manner that a period in which at least two flash memory devices simultaneously perform block erase operations, exists.

Abstract: An analog/digital (A/D) converter includes a sequential approximation register (SA register) having a plurality of bits for storing the results of conversion in digits and an incrementor having a smaller number of bits than that of the SA register. The incrementor increments a portion of the results of conversion on the basis of the result of conversion of at least one bit in the SA register so as to minimize an error in the A/D conversion of a smaller number of bits than that of the SA register.

Abstract: Even in the case where a microcomputer according to the present invention is directly connected to a bus in a LAN, it is possible to upgrade the data transfer speed of the LAN. When a built-in exclusive-OR circuit in the SIO of the microcomputer detects the discordance between a signal at an R.times.D terminal and a signal at a T.times.D terminal, a D flip-flop circuit generates and sends out an interrupt signal to the CPU. The CPU is made to recognize the collision of signals by the generation of the interrupt signal.

Abstract: A microcomputer comprising a clock circuit which selects a pulse signal as a system clock of the microcomputer from among a plurality of pulse signals and a power source impedance controlling circuit which controls an impedance between a power input terminal and the units of the microcomputer based on the frequency of the pulse signal selected by the clock circuit to provide the electric power to the units of the microcomputer. The power source impedance controlling circuit controls the impedance such that the power source impedance is made lower as the frequency of the selected pulse signal is higher.

Abstract: A data output portion transmits a pulse signal having a pulse width according to a value of transmit data on a predetermined cycle. An H pulse width counter and an L pulse width counter measure a length of a high level period and a length of a low level period in the received pulse signal by using a clock signal having the same frequency as that of the clock signal used in the data output portion. A comparing portion compares the sum of both the measured lengths of the periods with the predetermined cycle, and outputs an error signal in case of a mismatch. In a PWM communication system, it is also possible to detect a signal delay or an error of the clock signal, which is temporarily caused within one cycle.

Abstract: A semiconductor integrated circuit includes a first power system element group having an internal circuit for providing an output signal, and a second power system element group for receiving the output signal. An independently activated and deactivated power source potential is supplied to each of the first and second power system groups. In one embodiment of the invention, a fixing circuit maintains the level of the output signal from the internal circuit when the power source input potential to the first group is lowered or turned off. As a result, through currents in the nature of transitional large currents are reduced in the internal circuit elements of the second group.

Abstract: A digital/analog converting circuit wherein, on the digital signal input side of each of resistances D.sub.1, D.sub.2 . . . D.sub.n whose one end being connected to a digital signal input and the other end to an analog signal output, each of the three-state non-inverting buffers B.sub.1, B.sub.2 . . . B.sub.n is provided, and between the analog signal output side of the resistance D.sub.n and the ground potential portion, a MOS transistor 20 is provided. It enables to switch the output/non-output or an analog signal obtained by converting a digital signal, and as a result, a digital/analog converting circuit not generating non-linear region in the digital/analog conversion characteristic can be obtained.

Abstract: Disclosed herein is a semiconductor device package including a ground frame formed of a metal plate. The ground frame has a rectangular central portion, four legs integrally extending outward from the four corners of the central portion, and four grounding lead terminals formed integrally with the outer ends of the four legs. The width of each grounding lead terminal including a grounding portion is set to about three to five times the width of each lead terminal. The outer end of each grounding lead terminal is slightly projected outward from the outer end of each lead terminal. Accordingly, a stable ground potential can be ensured, and deformation of each lead terminal can be reliably prevented.

Abstract: According to a time required for programing operation, respective chips of flash memories are divided into a first group and a second group of chips requiring a time longer than the first group for the programing operation, and a postburn-in test, a high temperature test, and a low temperature test are carried out to a plurality of chips belonging to the first group simultaneously, and to a plurality of chips belonging to the second group simultaneously.

Abstract: In the region filling circuit of this invention, if only the starting position and the end position of the filling region rare supplied from outside, the inversion of bits in the filling area including the starting position and the end position where the whole bits are possibly not the subject of filling can be executed by hardware independently of a CPU, thereby to shorten the filling time and consequently reducing the time when the CPU is occupied during the filling.

Abstract: A sense amplifier circuit comprising a capacitor 12 having a capacity larger than a parasitic capacity 32 of a selected bit line 33, and a differential amplifier 30 for fixing, after the determination of the read data, the voltage level of the selected bit line to a level at which a read current does not flow through said selected bit line, or for cutting a quasi-write in current so as not to be flown into the selected memory cell, thereby the consuming current is reduced and damage of data due to quasi write in is prevented.

Abstract: A flash memory and its data refresh method, where data read out in program verify mode and erase verify mode from read address are compared in each address (ST110), and data of a memory cell corresponding to inconsistent data are rewritten (ST112). Or adding values of data read out in the program verify mode and the erase verify mode are compared in each block (ST137) and a defective block is retrieved and data in each address are compared in the defective block (ST160), and data of a memory cell corresponding to inconsistent data are rewritten (ST162). Thereby, defective data can be retrieved and corrected.

Abstract: A closed caption decoder with a pause function suitable for learning a language comprising: a closed caption decode circuit for decoding closed caption signals included in video signals outputted from a video cassette recorder and for outputting a detection signal when a predetermined control code is decoded; a timer which measures an elapse of time from a time when the predetermined control code is decoded; and a pause control circuit for instructing the caption decode means to perform a pause operation of caption decode and the video cassette recorder to perform a pause of video reproduction when the detection signal is outputted form the closed caption decode circuit and for outputting a pause termination signal of caption decode to the closed caption decoder and a pause termination signal of video reproduction to the video cassette recorder when the timer measures a predetermined period of time.

Abstract: An emulator probe comprising a direction changing board 10 having a first connector 11 to be coupled to a relaying connector 9 set on one surface thereof and a second connector 12 set on the other surface thereof such that the direction of setting of the same is different from the direction of setting of the first connector 11 and adapted such that soldering to a microcomputer mounting foot pattern 3 is achieved not through a pin terminal but through a semicircular edge portion of a semicircular through hole 8a formed in the peripheral surface of a semicircular through-hole board 8, and therefore, the emulator can be mounted on a user target board 1 easily without the need to deform the emulator cable and, further, the area occupied by the microcomputer mounting foot pattern can be decreased.

Abstract: A buffer circuit with driving current adjusting function is provided which may automatically set a driving current characteristics of a buffer to the most suitable value according to a system where the driving current is to be applied.

Abstract: In an EEPROM, a column decoder control register stores, in accordance with a first signal on a system bus, a state indicating whether one byte of bit lines or all of the bit lines are selected. When the column decoder control register stores the state for selecting all of the bit lines, a column decoder selects a full Y-gate so that the same data is latched in a full column latch by latching data once. The latched data is written by a controller into all bytes in a page.