Abstract: The detector includes a plug for connecting a personal computer through a cable, a battery power supply which provides a constant power supply, and an MCU which receives a specific potential from the personal computer when the latter is connected.

Abstract: The detector includes the plug for connecting the personal computer through a cable, battery power supply which provides a constant power supply, and the MCU which receives a specific potential from the personal computer when the later is connected.

Abstract: A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.

Abstract: A teletext data separation apparatus has a slice level generating circuit including a slice timing control circuit, a control register, an adder and a divider. The slice timing control circuit generates a timing signal for sampling. The control register carries out ON/OFF control of the slice timing control circuit. The control register sets by its register value the number of the sampling points of the adder and divider. By varying the register value in response to the reception state, the number of the sampling points can be increased from the specified 16 points, for example. This makes it possible for teletext data separation apparatus to generate an appropriate slice level that enables the teletext data to be separated reliably even in conditions where noise or distortion occurs in the video signal because of the effect of a weak electric field or ghost.

Abstract: An A/D converter updates its reference potential so that it coincides with an analog potential of a video signal. The A/D converter changes a variable voltage range of the reference potential during the same horizontal synchronizing period based upon a horizontal synchronizing signal. It is possible to correctly discriminate data superposed on the video signal even if an analog potential of the video signal considerably varies during the same horizontal synchronizing period.

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: The detector includes the plug for connecting the personal computer through a cable, battery power supply which provides a constant power supply, and the MCU which receives a specific potential from the personal computer when the later is connected.

Abstract: A power-residue calculating circuit includes: an I/F (interface) circuit with respect to an external bus; an e register holding a key e; a Y register holding a multiplier Y for Montgomery conversion; an N register holding a key N; a B2N register holding a value of (2B+N) calculated during the Montgomery conversion; an X register holding a plaintext X; a calculating circuit performing calculations for encryption and decryption; a P register holding a calculation result P; a power-residue control circuit serving as a state machine when the power-residue calculation is performed; a Montgomery multiplication residue/residue control circuit serving as a state machine when the Montgomery multiplication residue calculation and residue calculation are performed; and an addition/subtraction control circuit controlling calculations addition and subtraction.

Abstract: A semiconductor integrated circuit is capable of filling the need for more memory space through the effective use of an already-designed core block. A block (1) including a CPU, an array (4a) of a plurality of bonding pads, and RAMs (21a, 22a) which are first memories located on the same side of the array (4a) as the block (1) are already designed. The requirement for increased memory capacity can be filled with ease by the addition of RAMs (24a, 25a) which are second memories located on the opposite side of the array (4a) from the block (1). Since the second memories are different in physical configuration from the first memories, it is easy to design a physical configuration to achieve required memory capacity outside a core block (8a) within a single-chip microcomputer (9c).

Abstract: A screen display unit includes a display RAM to which a CPU writes palette codes corresponding to character codes, and a selector for selecting display color data read from one of two color palettes on a character code by character code basis in response to the palette codes read from the display RAM. The selector can select one of the two color palettes on a character code by character code basis, thereby making it possible to carry out display in a greater number colors on the same screen than the number of colors indicatable by the display color codes stored in the display RAM without increasing the capacity of a font data memory.

Abstract: An input circuit of a one-chip microcomputer is connected to an external switching circuit. When an analog input signal of a significant level generated in the external switching circuit is received at an analog input terminal of the input circuit, an A/D conversion start request signal is generated in an A/D conversion start request generating circuit and is sent to an A/D converter. The operation of the A/D converter is started in response to the A/D conversion start request signal, the analog input signal received at the analog input terminal is converted into digital data, and an A/D conversion finish signal is sent from the A/D converter to a CPU of the one-chip microcomputer. The operation of the CPU is started in response to the A/D conversion finish signal, and the digital data is readout to the CPU.

Abstract: A graphic accelerator includes an image-forming data decode unit, an image memory control unit and a screen data generation unit. The image memory control unit performs a control for writing an output of the image-forming data decode unit to a frame buffer and reading out information stored in the frame buffer. Screen data generation unit restores (interpolates) the color information based on the data read out from the frame buffer and generates screen data. In the frame buffer the information for each pixel is stored in a deleted form including two types of color information among three types of color information consisting of R, G and B. At the reading, the deleted color information is interpolated with the color information of other pixel.

Abstract: A plurality of core chips are arranged on a body of a semiconductor device, and a plurality of voltage down circuits are arranged on the outside of the core chips to lower a power supply voltage to a plurality of operating voltages of the core chips. In cases where the operating voltages differ from each other, each core chip is connected to the corresponding voltage down circuit. In cases where the operating voltages are the same as each other, one voltage down circuit corresponding to the same operating voltage is connected to a line surrounding the core chips, and the core chips are connected to the line. In cases where the operating voltage of one core chip is equal to the power supply voltage, the core chip is directly connected to a line of the power supply voltage.

Abstract: An MWL signal encoding part encodes a signal occurring on a main word signal line, an SD signal encoding part encodes a signal occurring on a subdecode signal line, a WL calculating part calculates a WL value, based on an MWL signal encoded value and an SD signal encoded value; an input and output operation part allows one-word data in a memory cell selected by the WL value to be read and written via the bit signal line; and a read and write control part controls a read operation and a write operation of the input and output operation part, based on a signal level on the bit signal line.

Abstract: A microcomputer includes a nonvolatile memory for storing contents that can be erased from and written to the nonvolatile memory electrically when an erasing/writing voltage is supplied to the nonvolatile memory, and a processor for executing a program stored in the nonvolatile memory. The microcomputer also includes a setting element for setting a plurality of conditions for erasing contents from or writing contents into the nonvolatile memory, and an erasing/writing voltage supply enabler for enabling the erasing/writing voltage to be supplied to the nonvolatile memory when all of the plurality of conditions are satisfied.

Abstract: A clock switchover circuit includes a NAND circuit supplied with an output of a first inverter circuit, and a first flip-flop (DFF) supplied with an output of the NAND circuit. Further, the circuit includes a NOR circuit, and a second DFF supplied with an output of the NOR circuit. A second inverter circuit is supplied with an output of the first DFF. A clock signal selection section is supplied with outputs of the second DFF and the second inverter circuit. A third inverter circuit is supplied with an output of the clock signal selection section and produces a clock signal.

Abstract: A CPU including a CPU-side signal line for connecting each of CPU-side memory device, OSD device, and OSD-side memory device to the CPU, and switching means for disconnecting the OSD device and OSD-side memory device from the CPU-side signal line when the CPU erases or rewrites memory contents of the CPU-side memory device through the CPU-side signal line.

Abstract: A non-contact IC card system capable of improving the data transmission rate and communication range without considerably enlarging the frequency band of a signal to be put to use. An AM-modulated signal (1F) from a reader writer (200) is received by a resonance circuit (6) of an IC card (100), and an IC card driving power source is produced therefrom in a rectifying section (8). In addition, it is demodulated in an AM demodulating circuit (10) and decoded in a decoder (13), thereby presenting reception data (10). On the other hand, when data (1J) is transmitted from the IC card (100), a characteristic of a regulator (9) for stabilizing an operating voltage of the resonance circuit (6) is altered on the basis of a signal encoded in an encoder (11) so that the signal is transmitted as an AM-modulated signal (1P) to the reader writer (200).

Abstract: In determining a level of a digital signal to be either “0” or “1” (0/1-determination), erroneous determination occurring under influences of a noise superimposed on an input signal is prevented. A data slicer (100) receives a video signal digitized by an A/D converter circuit (1), as an input signal. A 0/1-determining circuit (2) determines a level of the input signal relative to a predetermined reference level, and outputs a digital signal (A) based on a result of the determination. A control part (3) outputs a control signal (B) based on the digital signal (A). The predetermined reference level used in the 0/1-determination is switched between two levels by a first selector circuit (4), based on the control signal (B).

Abstract: An LSI with built-in CPU includes a CPU core, an internal CPU bus connected to the CPU core, an external memory access-use external pin for accessing an external memory and a bus selector for outputting signals of the internal CPU bus to the external memory access-use external pin when the external memory is not being accessed.