Abstract: A multi-level semiconductor device, the device including: a first level including a substrate; a second level including at least one photo detector, where the second level is disposed above the first level, and where the substrate includes at least one interconnect layer; an oxide layer disposed between the first level and the second level; at least one read out circuit, where the second level is bonded to the oxide layer; and a control circuit.

Abstract: A computing device including: a substrate level including at least one interconnect layer, which includes at least one first metal layer; a first level disposed on top of the substrate level and includes first transistors and at least one second metal layer; a second level including at least four independently controlled first memory arrays and includes second transistors; a third level disposed on top of the second level, where the third level includes second memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors and at least one third metal layer, where the fourth level includes third memory arrays; where the fourth level is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes at least one SRAM memory array, and where the substrate includes an area larger than 2,000 mm2.

Abstract: A 3D device, the device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; at least four functional units each including a first circuit and a second circuit; and a redundancy circuit, the first circuit including a portion of the first transistors, the second circuit including a portion of the second transistors, where each of the at least four functional units includes a vertical connectivity structure, the vertical connectivity structure including a plurality of pillars, where the plurality of pillars provides electrical control connection between the first circuit and the second circuit, where each of the at least four functional units includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, where the bonded includes metal to metal bonding regions.

Abstract: A computing device, including: a first level; a second level, where the first level includes a plurality of interconnect lines, where the second level is disposed above the first level and includes a plurality of processor arrays; and a memory structure disposed above the first level, where the memory structure includes a control level, a first array of memory cells overlaying the control level, and a second array of memory cells overlaying the first array of memory cells, where at least one of the plurality of interconnect lines connect over a distance of at least 40 mm, and where the plurality of processor arrays include at least one Graphic Processor Unit (“GPU”).

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a second level including a second single crystal silicon and a plurality of transistors, the second level is disposed over the second metal layer; a third metal layer disposed over the second level; a fourth metal layer disposed over the third metal layer; a via disposed through the second level, where the via has a diameter of less than 450 nm, where the second level thickness is less than four microns, and where the via includes contact to at least one of the plurality of transistors.

Abstract: Methods of making a 3D multilayer semiconductor device including: providing a first level with a first single crystal silicon layer (1stSCSL) and a second level including a 2ndSCSL; performing epitaxial growth of a first SiGe-layer on top of the 2ndSCSL; performing epitaxial growth of a 3rdSCSL on top of the first SiGe-layer, where the 3rdSCSL has an average thickness of less than 2,000 nm; forming first transistors each including a single crystal channel, where the forming of first transistors includes performing an epitaxial growth of a second SiGe-layer on top of the 3rdSCSL; forming metal layers interconnecting the first transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL, where at least one of the first transistors include at least one gate-all-around channel.

Abstract: A semiconductor device, the device including: a first silicon layer including first single crystal silicon; an isolation layer disposed over the first silicon layer; a first metal layer disposed over the isolation layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the isolation layer includes an oxide to oxide bond surface, where the plurality of transistors include a second single crystal silicon region; and a third metal layer disposed over the first level, where a typical first thickness of the third metal layer is at least 50% greater than a typical second thickness of the second metal layer, and where the first level includes an array of memory cells.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including a plurality of first metal layers; a second level overlaying the plurality of first metal layers, the second level including a second single crystal layer, a plurality of transistors, and a plurality of second metal layers, where at least one of the plurality of transistors includes a metal gate, where the second single crystal layer thickness is less than 2 microns, where the plurality of transistors includes one or more transistors with a first Threshold Voltage (Vt1), where the plurality of transistors includes one or more transistors with a second Threshold Voltage (Vt2), and where Vt1 is greater than Vt2.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal silicon layer; a second level including single crystal transistors, where the first level is overlaid by the second level; a transferred layer and a bonded layer, where the second level is bonded to the first level, where the second level includes a thickness less than 2 microns, and where the second level includes a plurality of memory cells; and a digital-to-analog converter, where the second level includes at least four memory arrays, and where each of the at least four memory arrays is independently controlled.

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; power decoupling capacitors; at least four functional units (FCUs); where each FCU includes a first circuit which includes a portion of the first transistors, and includes a second circuit which includes a portion of the second transistors, and includes a vertical connectivity structure (VCS), the VCS includes a plurality of pillars which provides electrical control connection between the first circuit and the second circuit. Each of the FCUs includes at least one memory control circuit and at least one memory array. The second level is bonded to the first level and includes metal to metal bonding regions. A third transistor and a fourth transistor are electrically connected and are at least 50 mm apart.

Abstract: A 3D semiconductor device, the device including: a first level including logic circuits; a second level including a plurality of connectivity units, where the first level is overlaid by the second level, where each of the plurality of connectivity units includes at least one receiver circuit; and horizontally oriented transmission lines, where at least one of the plurality of connectivity units includes an Orthogonal Frequency Division Multiple Access (“OFDMA”) modulation circuit.

Abstract: A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another of the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

Abstract: A 3D semiconductor device including: a first level including a single-crystal layer, a memory control-circuit including first transistors, a first metal layer, a second metal layer, a third metal layer; connection of the first transistors includes the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines, including at least four memory mini-arrays including at least four-rows-by-four-columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal-gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; a semiconductor die, including second transistors and at least one alignment mark positioned toward the die edge, disposed atop said first level.

Abstract: A method to process a semiconductor device: processing the substrate forming a first level with a first single-crystal silicon-layer, first transistors, input-and-output (“IO”) circuits; forming a first metal-layer; forming a second metal-layer including a power-delivery network, where interconnection of the first transistors includes the first metal-layer and the second metal-layer; processing a second level including second transistors with metal gates and a first array of memory-cells; processing a third level including a plurality of third transistors with metal gates and a second array of memory-cells; third level disposed over the second level; forming a fourth metal-layer over a third metal-layer over the third-level; processing a fourth level including a second single-crystal silicon-layer, fourth level is disposed over the fourth metal-layer; forming a via disposed through the second and third levels, connections of the device to external devices includes the “IO”-circuits; the second level is dispos

Abstract: A method for fabricating a semiconductor device comprising: forming a first level; disposing a second level on top of the first level; disposing a third level on top of the second level; forming a via connection through the second level and the third level, where the first level comprises first transistors, at least four independently controlled first memory arrays, and first filled holes therein, where the second level comprises second memory arrays and second filled holes therein, where disposing the third level comprises third transistors, a plurality of third memory arrays, and at least one metal layer therein; disposing a fourth level on top of the third level, where the fourth level comprises fourth transistors and at least one SRAM memory array therein; and bonding the fourth level to the third level via metal-to-metal bonding regions.

Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and/or the second, and/or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.

Abstract: Methods of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer (SCSL); providing a second substrate including a second level, the second level including a second SCSL; performing an epitaxial growth of a SiGe layer on top of the second SCSL; performing an epitaxial growth of a third SCSL on top of the SiGe layer, the third SCSL has an average thickness of less than 2,000 nm; forming second transistors each including a single crystal channel, where forming the second transistors includes growth of a second SiGe layer on top of the third SCSL; forming many metal layers interconnecting the second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the first single crystal transistors or second transistors include at least two FinFet transistors each having different threshold voltages.

Abstract: An integrated semiconductor device including: a first level including single crystal silicon and logic circuits each include first transistors; a second level, disposed above the first level and includes arrays of first memory cells, where the second level includes a plurality of second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; a plurality of SerDes circuits; and a third level, where the third level includes a plurality of third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate having an area greater than 1,000 mm2, and where the substrate includes at least one interconnect.

Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, and where the third level is bonded to the second level; a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors; and a plurality of capacitors, where the single crystal first transistors or the second transistors include at least two FinFet transistors, and where two of the at least two FinFet transistors have different threshold voltages (Vt).