Patents Assigned to Monolithic 3D Inc.
  • Publication number: 20240297169
    Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20240295691
    Abstract: A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits; a second level comprising at least one electromagnetic wave receiver, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said device comprises at least one read out circuit, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.
    Type: Application
    Filed: March 30, 2024
    Publication date: September 5, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 12080743
    Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of memory circuits.
    Type: Grant
    Filed: February 4, 2024
    Date of Patent: September 3, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 12080630
    Abstract: A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: September 3, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 12068187
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
    Type: Grant
    Filed: January 27, 2024
    Date of Patent: August 20, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20240274534
    Abstract: A method of making a 3D multilayer semiconductor device, the method comprising: providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer; providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer; forming a plurality of second transistors each comprising a single crystal channel; forming a plurality of metal layers interconnecting said plurality of second transistors; and then performing a bonding of said second level onto said first level, wherein performing said bonding comprises making oxide-to-oxide bond zones, and performing removal of a majority of said second single crystal silicon layer.
    Type: Application
    Filed: March 31, 2024
    Publication date: August 15, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Publication number: 20240274523
    Abstract: A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; a via disposed through the second level; the device includes at least one temperature sensor; the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.
    Type: Application
    Filed: April 1, 2024
    Publication date: August 15, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240260282
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one power down control circuit.
    Type: Application
    Filed: March 2, 2024
    Publication date: August 1, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Publication number: 20240260262
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer, a second metal layer overlaying the first metal layer, a plurality of second transistors disposed atop the second metal layer, a third metal layer disposed above the plurality of second transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one In-Out interface controller circuit.
    Type: Application
    Filed: March 4, 2024
    Publication date: August 1, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 12051674
    Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.
    Type: Grant
    Filed: March 14, 2024
    Date of Patent: July 30, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240250163
    Abstract: 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; second metal layer overlaying first metal layer; a second level including second transistors, first memory cells and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells and include at least one sense amplifier; third metal layer disposed above third level; fourth metal layer includes global power distribution grid, has a thickness at least twice the second metal layer, disposed above third metal layer; fourth level includes single-crystal silicon, atop fourth m
    Type: Application
    Filed: January 31, 2024
    Publication date: July 25, 2024
    Applicant: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Publication number: 20240251572
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and a memory control circuit, the memory control circuit including a plurality of first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer, a plurality of second transistors disposed atop the second metal layer; a third metal layer disposed atop the plurality of third transistors; and a memory array including word-lines and memory cells, where the memory array includes at least four memory mini arrays, where at least one of the plurality of second transistors includes a metal gate, where each of the memory cells includes at least one of the plurality of second transistors, and where the memory control circuit includes at least one digital to analog converter circuit.
    Type: Application
    Filed: February 29, 2024
    Publication date: July 25, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 12041791
    Abstract: A semiconductor device including: a first level including a plurality of first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; and a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes (FFHs), where the second level includes second filled holes (SFHs), where the SFHs are aligned to the FFHs with a more than 1 nm but less than 40 nm alignment error, where the third level includes a plurality of Look-Up-Table circuits.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: July 16, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 12041792
    Abstract: A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.
    Type: Grant
    Filed: March 14, 2024
    Date of Patent: July 16, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Patent number: 12033884
    Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one (ALO) second level on top of or above the second metal layer; performing a lithography step on the second level; forming ALO third level on top of or above the ALO second level; performing processing steps to form first memory cells within the ALO second level and second memory cells within the ALO third level, first memory cells include ALO second transistor, second memory cells include ALO third transistor, first metal layer thickness is at least 50% greater than the second metal layer thickness, ALO first transistor controls power delivery to ALO second transistor; then dicing using a laser system.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: July 9, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 12035531
    Abstract: A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit which includes a plurality of first transistors; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors which include a metal gate are disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; and a memory array including word-lines, the memory array includes at least four memory mini arrays, each including at least four rows by at least four columns of memory cells, where each of the memory cells includes at least one of the second transistors or at least one of the third transistors, the memory control circuit includes at least one Look Up Table circuit (“LUT”).
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: July 9, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Publication number: 20240222333
    Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240224545
    Abstract: A 3D memory device, the device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of temperature sensors, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Publication number: 20240222368
    Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.
    Type: Application
    Filed: March 13, 2024
    Publication date: July 4, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12027518
    Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.
    Type: Grant
    Filed: March 13, 2024
    Date of Patent: July 2, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist